Process

A process node designates a semiconductor technology generation, historically tied to minimum feature size but now primarily a marketing designation reflecting transistor density and performance improvements. Historical naming: referenced minimum gate length—350nm, 250nm, 180nm, 130nm, 90nm, 65nm had features matching the name. Modern reality: actual minimum features no longer match node name—"7nm" node has minimum metal pitch ~36nm and fin pitch ~30nm. What defines a node: (1) Transistor density—logic cells per mm²; (2) Performance—speed improvement over previous node (typically 10-15%); (3) Power—dynamic and leakage power reduction; (4) Area—die shrink for same function (typically 0.5-0.7× area). Node progression: planar MOSFET (180nm-28nm) → FinFET (22/16/14nm-5/3nm) → Gate-All-Around/nanosheet (3nm/2nm and beyond). Foundry naming examples: TSMC N7/N5/N3, Samsung 7LPP/5LPE/3GAE, Intel 7/4/3 (formerly 10nm/7nm). Half-node variants: N7+ (EUV), N5P (performance), N4 (density optimization)—incremental improvements within a node family. Scaling metrics: contacted poly pitch (CPP) and minimum metal pitch (MMP) are more meaningful than node name. Cost: each node increases per-transistor cost reduction but total mask/design cost rises significantly. Node selection: designers choose based on performance/power/area/cost trade-offs for target application. Process node advancement continues but with diminishing returns and increasing complexity, driving interest in heterogeneous integration as complementary scaling approach.