The 6T SRAM cell: two inverters that hold one bit by fighting each other Cross-coupled inverters latch the bit; two access transistors let the bitlines read or write it 1 · Six transistors a latch plus two gates WL (wordline) BL BL̄ M5 M6 INV A INV B Q Q̄ 4 latch FETs (M1–M4) + 2 access (M5,M6) Q and Q̄ always hold opposite values Two inverters wired output-to-input form a latch with two stable states. 2 · Read & write the wordline opens the door Hold (WL = 0) access FETs off; the latch feeds back on itself and keeps the bit forever — as long as the cell stays powered. static: no refresh needed. Read (WL = 1) precharge both bitlines high, raise WL; the storage node pulls one BL down a little; a sense amp resolves the bit. Write (WL = 1) drive the bitlines hard to the new value; the access FETs overpower the latch and flip Q / Q̄ to the written state. 3 · Why SRAM, and its cost fast and stable, but big Fast & static single-cycle access, no refresh — ideal for caches right next to the cores. Six transistors = area far larger per bit than DRAM’s 1T1C, so capacity is limited & expensive. Stability margins read must not disturb the bit; sizing ratios set read/write noise margins. The bitcell sets the SoC SRAM is often half a modern chip’s area. Foundries push a specially-drawn cell to the density limit each node; it drives cache size, cost and yield. Cross-coupled latch Two inverters hold Q and Q̄ — the bit is stored as a stable state. Access transistors The wordline gates the bitlines onto the node to read or write. Static, not stored charge Holds its bit with no refresh — but at six transistors per bit. SRAM Bitcell Scaling — the challenge of shrinking the basic SRAM memory cell at each technology node, often considered the most demanding layout challenge and the benchmark for process capability.
6T SRAM Cell
6 transistors per bit: 2 pull-up PMOS + 2 pull-down NMOS + 2 access NMOS Cross-coupled inverters store one bit (0 or 1) Access transistors controlled by word line Why SRAM Is the Benchmark
Contains the smallest transistors at minimum pitch in every dimension Tests the process at its absolute limits First structure to work (or fail) at a new node SRAM yield is a leading indicator of process maturity Bitcell Area Scaling
Node Bitcell Area Density 14nm 0.059 μm² ~17 Mbit/mm² 7nm 0.027 μm² ~37 Mbit/mm² 5nm 0.021 μm² ~48 Mbit/mm² 3nm 0.0199 μm² ~50 Mbit/mm²
Scaling Challenges
Read stability: Access transistor must not flip the cell during read Write-ability: Must be able to overwrite the cross-coupled inverters Leakage: 6 transistors × billions of cells = significant standby power Variability: Random dopant fluctuation (RDF) causes $V_{th}$ mismatch Alternatives
8T SRAM: Separate read port eliminates read-disturb. ~30% larger but more robust Gain cell (2T/3T): Smaller but needs refresh. Research stage SRAM bitcell area is the most commonly cited metric for comparing process technologies — it's the truest measure of a node's capability.