Wafer Fab

A wafer fab, short for fabrication facility, is the physical manufacturing plant where raw silicon wafers get transformed into finished integrated circuits through hundreds of individual process steps running over several weeks to months. Building and equipping a single leading-edge fab now routinely costs somewhere in the range of 10 to 20 billion dollars, which is exactly why fab economics — not just process technology — shapes essentially every major decision in the semiconductor industry, from which companies can afford to own fabs at all to where new ones actually get built.

Cleanroom classification — typically Class 1 to Class 10 for the most advanced fab areas, counting allowable particle density per cubic foot of air — isn't an arbitrary quality standard but a direct, physically necessary response to how small the features being patterned actually are, since a single stray particle landing on a wafer mid-process can easily be large enough relative to a modern transistor to cause a yield-killing defect. This is exactly why cleanroom specifications have tightened over successive technology generations in lockstep with shrinking feature sizes: a particle contamination level that was perfectly tolerable at an older, larger-geometry node can become a genuine yield problem at a newer node with proportionally smaller critical dimensions.

Wafer starts per month (WSPM) is the standard capacity metric for fab throughput, and leading-edge fabs running at 50,000 to 100,000 WSPM represent an enormous, continuous flow of wafers simultaneously moving through hundreds of different process steps at any given moment — not a batch-and-wait operation but a tightly scheduled, continuously flowing manufacturing line. This scale is exactly why fab capacity functions as a genuine macroeconomic constraint rather than just an internal operational metric: when WSPM capacity at leading nodes falls short of demand, that shortage directly constrains the supply of everything built on those nodes, AI accelerators very much included.

The foundry model — where companies like TSMC, Samsung, and GlobalFoundries manufacture chips designed by separate "fabless" companies such as NVIDIA, Apple, and AMD — exists specifically because owning and operating a leading-edge fab now requires a capital commitment in the tens of billions of dollars that very few companies can justify unless semiconductor manufacturing itself is their entire core business. This capital-intensity-driven separation between chip design and chip manufacturing is exactly why the industry has split into these two distinct business models — fabless design houses who never touch a wafer, and foundries who manufacture for dozens of different fabless customers simultaneously — rather than every chip company building and running its own fab the way the industry generally operated decades earlier.

Fab siting decisions weigh talent availability, supply-chain proximity, government incentive packages, water and power availability, and seismic stability all simultaneously, because a fab's enormous capital cost and multi-decade operating lifetime make every one of these location factors a genuinely consequential, hard-to-reverse decision rather than a minor logistical detail. Water availability in particular has become an increasingly visible constraint, since advanced wafer fabrication consumes very large volumes of ultra-pure water daily — a resource requirement that can itself rule out otherwise attractive fab locations in water-constrained regions.

Fab capacity at leading-edge nodes directly constrains the available supply of AI accelerator hardware, since every GPU, TPU, and custom AI chip ultimately traces back to wafer starts at one of a small handful of fabs capable of manufacturing at the node those chips require. This is exactly why AI hardware supply discussions inevitably circle back to fab capacity constraints rather than purely to chip design innovation — no amount of clever chip architecture matters if the physical wafer-fabrication capacity to actually manufacture that design at volume simply doesn't exist yet.