FinFET vs GAA

FinFET and GAA (Gate-All-Around) are the two transistor shapes the entire fab process you've just walked through was actually built to produce. Every step covered so far — litho patterning, plasma etch, CVD, ion implantation, CMP, interconnect — exists to build one thing at the bottom of the stack: a transistor that can switch cleanly between on and off. Old planar transistors, flat on the wafer surface with a gate sitting on top like a lid, ran into a hard physical limit as they shrank: the gate could only control the channel from one side, and below a certain size current started leaking through even in the "off" state. FinFET and GAA are two successive answers to that exact leakage problem, both solved by wrapping the gate around the channel from more directions.

FinFET stands the channel up on its edge so the gate can wrap around three sides of it instead of one. Instead of a flat channel with a gate resting on top, the channel becomes a thin vertical fin of silicon standing up from the wafer, and the gate material drapes over the top and down both sidewalls. That three-sided grip gives the gate far better electrostatic control over the channel, sharply cutting the leakage current that plagued shrinking planar transistors. FinFET became the industry's dominant transistor architecture starting around the 22nm–14nm generation and carried Moore's Law forward for over a decade.

FinFET vs. Gate-All-Around — Wrapping the Channel more gate surface touching the channel means tighter control over current leakage FinFET — 3-sided gate Gate-All-Around — 4-sided gate fin Gate wraps 3 sides of a raised silicon fin Gate fully surrounds each stacked nanosheet — all 4 sides More gate contact area = better electrostatic control GAA: width tunable per sheet As transistors shrink, wrapping the gate further around the channel is what keeps leakage under control.
Planar to FinFET to GAA: Wrapping the Gate Around the Channel Three cross-section panels showing the evolution from planar transistor (gate on one side) to FinFET (gate on three sides of a vertical fin) to GAA nanosheet (gate fully wrapping stacked horizontal channels on all four sides). PLANAR -> FINFET -> GAA: MORE GATE CONTROL EACH GENERATION PLANAR (older nodes) Gate touches channel on 1 side only Leaks badly once channel gets too short FINFET (~22-14nm era) Gate wraps 3 sides of a vertical fin Much better control, still 1 side open GAA NANOSHEET (current) Gate fully surrounds each stacked sheet — all 4 sides Best gate control, tunable WHY THIS TIES BACK TO EVERY STEP ALREADY COVERED Litho + etch pattern the fin/sheet stack -> a release etch removes sacrificial layers between nanosheets -> ALD/CVD deposits gate dielectric that must conformally coat suspended sheets on all sides -> ion implantation dopes the source/drain -> CMP flattens the gate stack before interconnect begins

GAA nanosheet transistors take the same idea one step further: instead of one vertical fin, the channel becomes several horizontal sheets stacked on top of each other, with the gate wrapping every side of every sheet. Building this shape adds a step that FinFET didn't need: after the fin/sheet stack is patterned, a selective "release etch" removes sacrificial layers between the silicon sheets, leaving them suspended like a tiny stack of shelves. Gate dielectric then has to conformally coat every sheet on all four sides — which is exactly the conformality problem the CVD/ALD entry described, just applied to a far more delicate structure. The payoff is worth the added complexity: full four-sided gate control is currently the best electrostatic grip achievable, and because each sheet's width can be tuned individually, designers get a knob over channel width that neither planar nor FinFET transistors ever had.

ArchitectureGate Contacts Channel OnIntroduced AroundMain AdvantageMain Challenge
Planar1 side (top)Long-standing, pre-2011Simple to manufactureSevere leakage below ~28nm
FinFET3 sides (top + 2 sidewalls)~22nm–14nmStrong leakage control, well-provenFin width/height set channel width — limited tunability
GAA Nanosheet4 sides (fully wrapped)~3nm and beyondBest electrostatic control, tunable sheet widthRelease etch + conformal fill add process complexity
Lithography and etch pattern the fin (FinFET) or sheet stack (GAA)
For GAA only, a selective release etch removes sacrificial layers between nanosheets
Gate dielectric deposited conformally around every exposed channel surface (ALD/CVD)
Gate metal fill completes the wraparound gate structure
Ion implantation forms source/drain regions at the channel ends
CMP planarizes the gate stack before interconnect layers begin
Transistor complete with full gate control over the channel

Every process step covered in this whole series exists to build this one structure correctly. An AI accelerator's raw compute density and power efficiency both trace back to how tightly the gate controls its channel — better control means the transistor can be driven at lower voltage for the same performance, which is where a huge share of a modern chip's power budget comes from. That's why the industry keeps pushing past FinFET into GAA nanosheets, and why even more exotic shapes like stacked complementary FETs (CFETs) are already being researched as the logical next step once nanosheet stacking itself reaches its own limits.

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