What Is Line Edge Roughness
Line edge roughness, or LER, refers to the small, irregular waviness along the edges of a patterned feature on a chip — instead of a perfectly smooth, straight line, real manufactured edges have tiny random variations, and controlling how much of that roughness exists is an important measure of manufacturing precision, especially as features shrink.
Line edge roughness matters more as features shrink because the same absolute amount of roughness becomes a much larger relative variation. A small amount of edge irregularity that would be negligible on a larger, older-generation feature becomes a much more significant fraction of a modern, much smaller feature's total width — this is why controlling LER has become an increasingly important manufacturing concern as chip features have continued shrinking generation after generation.
| Concept | What it describes |
|---|---|
| Line edge roughness (LER) | Random irregularity along a single patterned edge |
| Line width roughness (LWR) | Variation in overall feature width caused by roughness on both edges |
| Why it matters more at smaller nodes | Same absolute roughness is a larger fraction of a smaller feature |
LER originates largely from the photoresist itself, since the chemical process that develops the resist pattern isn't perfectly uniform at the molecular level. The chemical reactions and development process that create a photoresist pattern involve some inherent randomness at extremely small scales, which translates directly into small irregularities along the resulting pattern's edges — this is why improving photoresist chemistry and processing has been an important focus for reducing LER as feature sizes continue shrinking.
Excess line edge roughness can measurably affect transistor performance and consistency, not just look imperfect under a microscope. A transistor's electrical behavior depends on its precise physical dimensions, so irregular edges can cause small, random variations in a transistor's actual width along its length — these variations can translate into inconsistent electrical performance across what should be identical transistors on the same chip, which is why LER control is treated as a meaningful manufacturing quality metric, not just a cosmetic detail.
Measuring and controlling LER requires the same kind of specialized, high-precision metrology used for measuring critical dimension. Because LER involves irregularities smaller than what ordinary optical measurement can resolve, characterizing it accurately requires specialized techniques like electron microscopy, similar to the tools used for measuring critical dimension — LER and critical dimension control are closely related manufacturing quality concerns, both requiring the same class of specialized, high-precision measurement capability.
Read line edge roughness through a magnified-imperfection lens: it's a reminder that even the most precise manufacturing process still produces edges with some small, random irregularity at a close enough look — and as chip features keep shrinking, that same small irregularity becomes a proportionally bigger deal, making its control an increasingly important part of chip manufacturing quality.