Semiconductor Devices

A semiconductor device is the smallest structure on a chip that does something electrically useful on its own: a diode that passes current one way, a transistor that switches or amplifies, a memory cell that holds a bit, a sensor that turns light or pressure into charge. Everything above it — logic gates, cores, accelerators — is an arrangement of these few primitives repeated up to hundreds of billions of times on one die. The device is the layer where materials science stops being chemistry and becomes a controllable switch.

The loop in the middle is the whole history of device engineering: each shrink costs the gate some authority over the channel, and each new geometry is a way of buying that authority back.

A transistor is a valve, and the gate is the handle. A MOSFET has a source and a drain separated by a channel, with a gate sitting over that channel behind a thin insulator. Voltage on the gate inverts the surface of the channel and lets current flow; remove it and the valve closes. Nothing physically moves, which is why a transistor can switch billions of times per second without wearing out. Threshold voltages on modern logic sit around 0.2–0.4 V against a supply near 0.75 V, so the margin between "off" and "on" is a few hundred millivolts — the entire reliability of digital computing rests on holding that gap.

The 60 mV/decade limit is the reason voltage scaling stopped. How sharply a transistor turns off is measured by its subthreshold swing, and thermal statistics put a floor under it:

Every decade of off-current you want to remove costs at least 60 mV of gate swing. That floor is why supply voltage could not keep falling with feature size, why Dennard scaling ended in the mid-2000s, and why power — not area — became the binding constraint on chip design.

Short-channel effects are why the geometry keeps changing. Below roughly 25–30 nm of gate length, a planar MOSFET's drain field reaches far enough into the channel to switch it on without help from the gate: threshold voltage drifts with drain bias, off-state leakage climbs, and the device stops behaving like a switch. FinFETs, in volume from Intel's 22 nm generation in 2011, raise the channel into a fin and wrap the gate around three sides of it. Gate-all-around nanosheet devices — Samsung's 3 nm in 2022, TSMC's N2 and Intel's RibbonFET generation after it — stack two to four horizontal sheets and surround each one completely. CFET, which stacks the n-type device directly on top of the p-type, is the next rung, and it buys area rather than control.

CMOS is the reason a chip is not a space heater at idle. Pair an n-type and a p-type transistor so that one is always off, and the cell draws essentially no current except while it is switching. What it does draw follows a short equation that has driven every architectural decision of the last twenty years:

The square on voltage is why supply fell from 5 V in the 1990s to around 0.75 V today, and why — once that fall stalled against the 60 mV/decade floor — the industry had to buy performance with parallelism and specialised datapaths instead of clock frequency. A modern GPU is wide and relatively slow for exactly this reason.

Memory cells trade speed, density and retention against each other. An SRAM cell is six transistors holding a latch: fast, logic-compatible, volatile, and by far the largest per bit, which is why on-die cache is scarce and expensive. A DRAM cell is one transistor and one capacitor, far denser, but the charge leaks and every cell must be refreshed every few tens of milliseconds. NAND flash traps charge in an isolated layer and keeps it for years with no power, stacked now past 200–400 word-line layers, at the cost of slow, block-granular writes and finite endurance. Three different physical mechanisms, three different jobs — and the memory hierarchy in every system is just these trade-offs arranged in order.

Power and analog devices optimise for the opposite of logic. A logic transistor wants minimum area and capacitance; a power device wants to block hundreds of volts and carry tens of amps with minimum resistance. That favours wide-bandgap materials: silicon carbide and gallium nitride have critical breakdown fields near 3 MV/cm against silicon's roughly 0.3, so an equivalent device can be about ten times thinner and dramatically lower in on-resistance. SiC now dominates 800 V electric-vehicle traction inverters and GaN dominates compact chargers and high-density power supplies. Analog and RF devices, meanwhile, care about matching, noise and linearity rather than density, which is why high-value analog parts are still built happily on 180 nm and 65 nm processes.

A device only becomes useful to the layer above once it has been reduced to a compact model and a characterised cell library. That package — not the transistor itself — is what a design team consumes, and it is why a process node is delivered as a PDK rather than as a physics result.

Next in the stack is chip design. A single transistor computes nothing. Arranging billions of them — through architecture, RTL, verification, synthesis and place-and-route — into something that computes, stores and communicates is the subject of chip design, and it is where the characterised cell library above gets consumed.

Read a semiconductor device through an *electrostatic-control* lens rather than a *feature-size* lens: the figure of merit is how completely the gate owns its channel, measured by subthreshold swing against that 60 mV/decade floor and by how little current leaks when the device is off. Every geometry change in the last fifteen years — fin, nanosheet, stacked CFET — buys back control that the shrink gave away, and every material change at the power end of the market is the same argument conducted with breakdown field instead of gate length. The node number tells you the pitch; the electrostatics tell you whether the switch still works.