2,700 technical terms and definitions
fairchild 1963 fixed area cost recurring power cost compound, cmos transistor 1963 gate count under power budget finally real, silicon cmos 1963 completes figure of merit 1962 could not
Classify and Release: The Architecture Digital Logic Will Standardize On 1. Why This Series' Figure of Merit Finally Delivers What 1962's Own Could Not This closing step…
photodiode process sensor, pinned photodiode formation, transfer gate pixel, deep trench isolation sensor
A CMOS image sensor converts incident photons into a per-pixel electrical signal by pairing a pinned photodiode with a transfer-gate readout chain, and every process choice…
cmos image sensor dark current drift prediction, cmos image sensor, image sensor dark, sensor dark current, dark current drift, current drift prediction, cmos image
CMOS Image Sensor Dark Current Drift Prediction with Machine Learning Introduction & Motivation CMOS Image Sensor Dark Current Drift Prediction with Machine Learning addresses…
cmos image sensor microlens alignment prediction machine learning, cmos image, sensor microlens alignment, cmos, cmos image sensor microlens alignment prediction
CMOS Image Sensor Microlens Alignment Prediction with Machine Learning Introduction & Motivation CMOS Image Sensor Microlens Alignment Prediction with Machine Learning addresses…
cis, 4t pixel, image sensor, rolling shutter, global shutter
CMOS image sensor is a semiconductor imager that converts photons into pixel charge and reads arrays with CMOS circuits. CMOS image sensors serve phones, scientific cameras…
cmos image sensor pixel defect prediction machine learning, cmos image, sensor pixel defect, cmos, cmos image sensor pixel defect prediction, cmos image sensor, image sensor
CMOS Image Sensor Pixel Defect Prediction with Machine Learning Introduction & Motivation CMOS Image Sensor Pixel Defect Prediction with Machine Learning addresses a central…
process integration, gate-first gate-last, strain engineering, FinFET nanosheet GAA CFET, device architecture evolution, replacement metal gate, standard cell scaling, foundry process complexity, node transition
CMOS integration schemes are the overall architectural strategies that define how complementary NMOS and PMOS transistors actually get built together on the same substrate…
prevention, design, process, guard ring, well tap
CMOS latch-up constitutes the destructive, self-sustaining low-impedance state triggered by the regenerative turn-on of parasitic bipolar junction transistors inherent to bulk…
cmos logic 1980s step 19 74hc 74hct close the loop cmos retakes glue logic from ttl, 74hc 74hct close the loop cmos retakes glue logic from ttl
The 4000-Series Proves the Concept, 74HC/74HCT Close the Loop: CMOS Retakes Glue Logic From TTL 1. Why a Decade of "Too Slow to Matter" Finally Stopped Being True Steps 1 through…
cmos logic 1980s step 2 build a well to host the opposite device type, build a well to host the opposite device type
Build a Well: Hosting One Transistor Type Inside a Substrate Doped for the Other, Reversed Locally Rather Than Across the Whole Wafer 1. Why One Wafer Now Has to Carry Two…
cmos logic 1980s step 10 classify and release the cmos architecture standard, classify and release the cmos architecture standard
Classify and Release: The Architecture Digital Logic Will Standardize On 1. Why This Series' Figure of Merit Finally Delivers What 1962's Own Could Not This closing step…
cmos logic 1980s step 18 classify what later cmos generations inherit, classify what later cmos generations inherit
Classify and Close: What Later CMOS Generations Keep, and What Belonged Only to 1980 1. Separate the Enduring Abstraction From This Generation's Particular Numbers Every step…
cmos logic 1980s step 20 cmos becomes the default vlsi microprocessors and lasting dominance, cmos becomes the default vlsi microprocessors and lasting dominance
CMOS Becomes the Default: VLSI, Microprocessors, and a Dominance That Outlasts 1980s Numbers 1. Why the Inverter's Own Transfer Curve Is the Reason Density Scaled at All Every…
cmos logic 1980s step 16 complete the cmos vs hmos power delay density comparison, complete the cmos vs hmos power delay density comparison
Pay Every Cost Back Into the Comparison That Started This Series 1. Rebuild Step 11's Comparison With Every Term This Series Has Since Added Step 11 opened this series with…
cmos logic 1980s step 14 confront simultaneous switching noise and power distribution, confront simultaneous switching noise and power distribution
Confront the Current Spike: Why CMOS's Clean Power Term Creates a Dirty Power Grid 1. Contrast the Current Waveform CMOS Actually Draws Against the One NMOS Always Drew Step 11…
cmos logic 1980s step 7 confront the parasitic thyristor failure mode, confront the parasitic thyristor failure mode
Confront a Failure Mode the Well Itself Makes Possible: A Parasitic Thyristor Hiding Inside Every Complementary Pair 1. Why the Same Structure That Enables This Series Also…
cmos logic 1980s step 4 define source and drain for both transistor types, define source and drain for both transistor types
Define Source and Drain for Both Transistor Types: Two Diffusions That Must Never Touch Each Other's Territory 1. Why This Wafer Needs Two Masking Sequences Where Every Earlier…
cmos logic 1980s step 3 diffuse the well to the depth devices need, diffuse the well to the depth devices need
Diffuse the Well to the Depth Devices Actually Need: The Same Lateral-Spread Fact, a Much Bigger Number This Time 1. Why a Deep Diffusion Costs Far More Chip Area Than a Shallow…
cmos logic 1980s step 8 measure the switching power delay tradeoff, measure the switching power delay tradeoff
Measure Switching Power and the Power-Delay Trade-Off: The Power Step 6 Never Claimed to Eliminate 1. Why Near-Zero Static Power Was Never the Whole Picture This step measures…
cmos logic 1980s step 13 pay the guard ring area penalty for latchup prevention, pay the guard ring area penalty for latchup prevention
Pay for Safety in Silicon Area: What a Guard Ring Actually Costs 1. Turn the Loop-Gain Condition Into a Layout Rule Step 12 established that latchup triggers when , and that…
cmos logic 1980s step 9 qualify against single channel mosfet, qualify against single channel mosfet
Qualify Against the Single-Channel MOSFET Just Completed: More Area, More Steps, a Power Advantage 1962 Could Never Offer 1. Why This Series' Own Gate Costs More to Build Before…
cmos logic 1980s step 15 size decoupling capacitance against the switching noise budget, size decoupling capacitance against the switching noise budget
Size a Local Reservoir of Charge So the Grid Never Has to Answer Instantly 1. Separate What the Grid Can Supply Quickly From What a Transition Demands Instantly Step 14 showed…
cmos logic 1980s step 11 static power crosses the line nmos could not defend, static power crosses the line nmos could not defend
Why a Current That Never Turns Off Becomes the Deciding Term NMOS Cannot Scale Away 1. Separate the Power Term HMOS Could Manage From the One It Could Not HMOS pushed the NMOS…
cmos logic 1980s step 17 test the margin against hmos ii specifically, test the margin against hmos ii specifically
Run the Harder Test: Does the Margin Survive Against NMOS's Best Possible Answer 1. Substitute HMOS-II's Numbers for First-Generation HMOS's Step 16 confirmed CMOS's power…
cmos logic 1980s step 12 twin well cmos reintroduces the latchup density penalty, twin well cmos reintroduces the latchup density penalty
Build Two Wells on One Substrate, and Confront the Parasitic Transistor Density Reintroduces 1. State What Housing Both Device Types on One Substrate Actually Requires…
cmos logic 1980s step 1 two opposing transistors solve the power problem, two opposing transistors solve the power problem
Why Two Opposing Transistors Solve the Power Problem 1962 Closed On: Zero Current, Not Just Zero Gate Current 1. Why a Near-Zero Gate Current Was Never the Whole Answer This step…
cmos logic 1980s step 6 verify near zero static current in both states, verify near zero static current in both states
Verify Near-Zero Static Current in Both Logic States: Not Exactly Zero, But Orders of Magnitude Away From the Alternative 1. Why Step 1's Equation Finally Needs a Number Behind It…
cmos logic 1980s step 5 wire the pair into the first two transistor gate, wire the pair into the first two transistor gate
Wire the Pair Into This Project's First Two-Transistor Logic Gate: The Resistor 1960 Had to Size, This Gate Doesn't Need at All 1. Why This Gate Needs No Component This Project…
cmos fabrication, cmos manufacturing, cmos technology, cmos basics, cmos flow
CMOS process (complementary metal-oxide-semiconductor process) is the manufacturing technology that builds both NMOS and PMOS transistors on the same silicon substrate to create…
rf switch fom, soi rf switch, bulk acoustic wave baw filter, rf front end integration
CMOS RF switch process integrates a silicon-on-insulator stack with series-stacked field-effect transistors to route radio-frequency signals between antenna, filter…
static power dynamic power idd vdd ratioed nmos inverter, cmos crossover density clock speed decide nmos versus cmos cost, 1980 cmos twin well latchup density penalty becomes affordable
Why a Current That Never Turns Off Becomes the Deciding Term NMOS Cannot Scale Away 1. Separate the Power Term HMOS Could Manage From the One It Could Not HMOS pushed the NMOS…
twin well cmos independent n well p well tuning, parasitic pnp npn thyristor latchup loop gain beta, guard ring substrate tie layout area cost latchup prevention
Build Two Wells on One Substrate, and Confront the Parasitic Transistor Density Reintroduces 1. State What Housing Both Device Types on One Substrate Actually Requires…
guard ring n well p well tied vdd ground minority carrier, latchup trigger current effective substrate resistance, guard ring perimeter area cost small cell density penalty
Pay for Safety in Silicon Area: What a Guard Ring Actually Costs 1. Turn the Loop-Gain Condition Into a Layout Rule Step 2 established that latchup triggers when , and that…
ground bounce vdd droop di dt parasitic inductance cmos, cmos pulsed current waveform versus nmos steady i_dd, decoupling capacitance power grid design switching noise budget
Confront the Current Spike: Why CMOS's Clean Power Term Creates a Dirty Power Grid 1. Contrast the Current Waveform CMOS Actually Draws Against the One NMOS Always Drew Step 1…
decoupling capacitor local charge reservoir transient current, on chip mim capacitor placement wire inductance l_wire, guard ring versus decoupling cap two area taxes density cost
Size a Local Reservoir of Charge So the Grid Never Has to Answer Instantly 1. Separate What the Grid Can Supply Quickly From What a Transition Demands Instantly Step 4 showed that…
guard ring decap cost added back into power density comparison, cmos total power survives full cost accounting versus hmos, 1980s representative values watts gates per die cmos margin
Pay Every Cost Back Into the Comparison That Started This Series 1. Rebuild Step 1's Comparison With Every Term This Series Has Since Added Step 1 opened this series with…
hmos ii static term unchanged by scaling i_dd structural, cmos margin narrows numerically widens structurally scaling headroom, nmos physical limit versus cmos still has room to scale
Run the Harder Test: Does the Margin Survive Against NMOS's Best Possible Answer 1. Substitute HMOS-II's Numbers for First-Generation HMOS's Step 6 confirmed CMOS's power…
complementary topology eliminates power term structurally not process, density reactivates latent parasitic general scaling lesson, verdict series versus fabrication series 1963 device 1980 proof
Classify and Close: What Later CMOS Generations Keep, and What Belonged Only to 1980 1. Separate the Enduring Abstraction From This Generation's Particular Numbers Every step…
chemical mechanical planarization, chemical mechanical polishing, CMP planarization, polishing, Preston equation, slurry, abrasive, STI CMP, Cu CMP, W CMP, copper CMP, tungsten CMP, oxide CMP, dishing, erosion, endpoint detection, WIWNU, post-CMP clean
Chemical mechanical planarization is the only semiconductor manufacturing step that simultaneously exploits chemistry and abrasion to remove material, and it is the only step…
Copper Damascene, polishing, planarization, preston law, slurry chemistry
Chemical Mechanical Planarization is the critical nanomanufacturing process that unites chemical surface passivation and mechanical abrasive abrasion to achieve global and local…
cmp, substrate
A chip is built up as dozens of stacked layers, and every one of them has to start almost perfectly flat. Photolithography focuses its pattern onto a razor-thin plane; if…
design
CMP-aware routing is a physical design technique that considers Chemical Mechanical Planarization (CMP) effects during wire routing — adjusting layout choices to minimize…
cmp carrier film membrane fatigue prediction, cmp carrier film, carrier film membrane, film membrane fatigue, membrane fatigue prediction, cmp carrier, carrier film
CMP Carrier Film Membrane Fatigue Prediction with Machine Learning Introduction & Motivation CMP Carrier Film Membrane Fatigue Prediction with Machine Learning addresses a central…
cmp carrier retaining ring degradation prediction, cmp carrier retaining, carrier retaining ring, retaining ring degradation, ring degradation prediction
CMP Carrier Retaining Ring Degradation Prediction with Machine Learning Introduction & Motivation CMP Carrier Retaining Ring Degradation Prediction with Machine Learning addresses…
cmp slurry selectivity, copper cmp process, cmp dishing erosion, cmp endpoint detection
Chemical Mechanical Planarization is the critical nanomanufacturing process that unites chemical surface passivation and mechanical abrasive abrasion to achieve global and local…
cmp conditioner disk wear prediction machine learning, cmp conditioner, disk wear prediction, cmp conditioner disk wear prediction, cmp conditioner disk, conditioner disk wear
CMP Conditioner Disk Wear Prediction with Machine Learning Introduction & Motivation CMP Conditioner Disk Wear Prediction with Machine Learning addresses a central problem in CMP…
cmp diamond disk wear life prediction, cmp diamond disk, diamond disk wear, disk wear life, wear life prediction, cmp diamond, diamond disk, disk wear, wear life, life prediction
CMP Diamond Disk Wear Life Prediction with Machine Learning Introduction & Motivation CMP Diamond Disk Wear Life Prediction with Machine Learning addresses a central problem…
cmp dishing erosion, cmp dishing minimization, oxide dishing, metal dishing, copper dishing, cmp planarity, cmp topography, cmp
CMP dishing is the undesirable formation of a concave recessed surface profile in metal interconnect lines during chemical mechanical planarization, occurring when the polishing…
cmp dishing, copper cmp non uniformity, cmp pattern density effect, oxide cmp uniformity, cmp
CMP dishing is the undesirable formation of a concave recessed surface profile in metal interconnect lines during chemical mechanical planarization, occurring when the polishing…
cmp dishing and erosion prediction, cmp dishing erosion, dishing erosion prediction, cmp dishing, dishing erosion, erosion prediction
CMP Dishing and Erosion Prediction with Machine Learning Introduction & Motivation CMP Dishing and Erosion Prediction with Machine Learning addresses a central problem in copper…