CMOS Integration Schemes

CMOS integration schemes are the overall architectural strategies that define how complementary NMOS and PMOS transistors actually get built together on the same substrate — the specific sequence of process steps, materials choices, and structural decisions that together define an entire technology generation, rather than any single process step in isolation. Two fabs can both claim to build "7nm CMOS" while making genuinely different integration-scheme choices underneath that label, and those choices are exactly what separates one foundry's performance and cost profile from another's at the same nominal node.

The gate-first versus gate-last decision determines whether the final gate material has to survive the high-temperature source/drain activation anneal, or whether it gets formed only after that thermal step is already complete — and this single choice cascades into which gate materials are even usable at all. Gate-first integration forms the actual gate stack before source/drain activation, which means that gate stack has to tolerate the full thermal budget of everything that comes after it; gate-last (replacement metal gate) integration instead builds a sacrificial dummy gate first, runs the high-temperature steps, then removes the dummy and deposits the final metal gate into the resulting cavity — sidestepping the thermal-budget constraint entirely, at the cost of a more complex removal-and-refill sequence.

Strain engineering — compressively strained embedded SiGe source/drain regions for PMOS, tensile capping liners for NMOS — directly manipulates each transistor type's channel mobility by deliberately distorting its crystal lattice, and the specific combination chosen is itself a core integration-scheme decision rather than an afterthought bolted onto a finished transistor design. Because PMOS and NMOS respond to opposite strain directions — PMOS wants compression, NMOS wants tension — a CMOS integration scheme has to simultaneously deliver both strain types to immediately adjacent transistors on the same substrate without either strain-inducing step damaging the other transistor type, which is exactly the kind of process-sequencing puzzle that defines a mature CMOS integration scheme's complexity.

The planar-to-FinFET-to-nanosheet/GAA-to-CFET device architecture progression represents each generation's integration scheme reaching the scaling limit of its predecessor's fundamental geometry, forcing a genuinely new three-dimensional transistor structure rather than simply shrinking the previous structure's dimensions further. Planar transistors ran out of effective gate control over the channel as dimensions shrank, which FinFETs solved by wrapping the gate around three sides of a vertical fin; nanosheet/gate-all-around structures extended that same gate-control logic to wrap the gate around all four sides of a horizontal channel sheet; CFET pushes further still by stacking NMOS and PMOS transistors vertically on top of each other rather than side by side — each transition driven by the previous architecture hitting a hard physical scaling ceiling, not by an arbitrary roadmap decision.

Integration complexity translates directly into fab cost, cycle time, and achievable yield, because every additional strain-engineering step, every additional masking layer required by a more complex gate scheme, and every additional process module required by a newer device architecture adds both direct processing cost and additional opportunity for yield-limiting defects to occur. This is exactly why the choice of integration scheme is as much an economic decision as a technical one — a foundry adopting gate-all-around nanosheet transistors is accepting meaningfully higher process complexity and cost in exchange for performance and density gains that planar or FinFET architectures could no longer deliver at that node.

CMOS integration scheme choices connect directly to downstream process techniques covered elsewhere in this glossary — the [self-aligned contact process](self-aligned-contact-process) that most modern gate-last integration schemes depend on, and [contact-over-active-gate](contact-over-active-gate-integration) techniques that only became viable once self-aligned contacts matured enough to support them — illustrating how a single high-level integration-scheme decision ripples downward into which specific process techniques become necessary, or even possible, at the transistor-contact level.