27,049 technical terms and definitions
gpipe, pipedream, micro batch pipeline, model pipeline stage
Pipeline parallelism is a model-parallel strategy that partitions a neural network by depth into consecutive stages, placing each stage's layers on a different GPU. A batch flows…
model pipeline parallel, gpipe pipeline, micro batch pipeline, pipeline bubble overhead
Pipeline Parallelism is the distributed deep learning parallelism strategy that partitions a neural network into sequential stages across multiple GPUs, where each GPU computes…
model parallelism pipeline, gpipe pipeline, microbatch pipeline, pipeline bubble overhead
Pipeline Parallelism for Deep Learning is the distributed training strategy that partitions a neural network's layers across multiple GPUs in a sequential pipeline — with each GPU…
gpipe pipeline schedule, 1f1b pipeline schedule, pipeline bubble overhead, micro batch pipeline parallelism
Pipeline Parallelism for Deep Learning is the model parallelism strategy that partitions neural network layers across multiple GPUs in a sequential pipeline, processing different…
gpipe pipeline schedule, pipeline bubble overhead, microbatch pipeline training, interleaved 1f1b pipeline
Pipeline Parallelism in Deep Learning is the model partitioning strategy that assigns different layers (stages) of a neural network to different GPUs, flowing microbatches through…
gpipe pipeline stages, micro batch pipeline schedule, pipeline bubble overhead, interleaved pipeline 1f1b
Pipeline Parallelism for LLM Training is a model parallelism strategy that partitions a large neural network into sequential stages assigned to different devices, processing…
gpipe schedule, 1f1b pipeline schedule, pipeline bubble overhead, inter stage activation
Pipeline Parallelism is a model parallelism technique that divides neural network layers across multiple devices, enabling concurrent forward and backward passes on different…
pipeline parallelism stage distribution and bubble minimization, pipeline parallelism stage, parallelism stage distribution, stage distribution bubble, parallelism stage
Pipeline Parallelism Stage Distribution and Bubble Minimization Introduction & Motivation Pipeline Parallelism Stage Distribution and Bubble Minimization addresses a central…
pipeline model parallelism, gpipe pipedream, pipeline scheduling strategies, micro batch pipeline
Pipeline Parallelism is the model parallelism technique that partitions neural network layers across multiple devices and processes multiple micro-batches concurrently in…
model parallelism pipeline, gpipe training, pipeline bubble, micro batch pipeline
Pipeline Parallelism is the model parallelism technique that partitions neural network layers across multiple devices and processes micro-batches in a pipelined fashion — enabling…
pipeline stage handoff and flow control pattern, pipeline stage handoff, stage handoff flow, handoff flow control, flow control pattern, pipeline stage, stage handoff, handoff flow
Pipeline Stage Handoff and Flow Control Pattern Introduction & Motivation Pipeline Stage Handoff and Flow Control Pattern addresses a central problem in design process control…
pipelined adc inter-stage gain error prediction, pipelined adc inter-stage, adc inter-stage gain, inter-stage gain error, gain error prediction, pipelined adc
Pipelined ADC Inter-Stage Gain Error Prediction with Machine Learning Introduction & Motivation Pipelined ADC Inter-Stage Gain Error Prediction with Machine Learning addresses…
pipelined architecture pipeline depth prediction, pipelined architecture pipeline, architecture pipeline depth, pipeline depth prediction, pipelined architecture
Pipelined Architecture Pipeline Depth Prediction with Machine Learning Introduction & Motivation Pipelined Architecture Pipeline Depth Prediction with Machine Learning addresses…
piqa, evaluation
PIQA (Physical Intuition Question Answering) is the benchmark dataset that evaluates physical commonsense reasoning — testing whether AI models understand how physical objects…
piqa, evaluation
PIQA is a benchmark for physical commonsense reasoning about everyday interactions and feasible actions - It is a core method in modern AI evaluation and safety execution…
piranha bath organic removal saturation prediction, piranha bath organic, bath organic removal, organic removal saturation, removal saturation prediction
Piranha Bath Organic Removal Saturation Prediction with Machine Learning Introduction & Motivation Piranha Bath Organic Removal Saturation Prediction with Machine Learning…
rca clean, wafer cleaning, surface preparation, sc-1, sc-2, piranha clean, marangoni drying, clean tech
RCA cleaning and advanced semiconductor surface preparation constitute the sequential wet chemical and physical processes engineered to remove organic residues, sub-micron…
lithography pitch, contacted poly pitch, cpp, minimum metal pitch, mmp, feature pitch, pattern pitch, semiconductor pitch, node scaling, lithography
Lithography pitch is the fundamental center-to-center distance between repeating identical features on a semiconductor wafer, defining the ultimate packing density, interconnect…
manufacturing operations
Pitch is the planned production interval for a fixed pack quantity aligned to takt and container size - It provides a practical pacing unit for shop-floor control. What Is Pitch?…
advanced packaging
Pitch Scaling in Advanced Packaging is the progressive reduction of interconnect pitch (center-to-center distance between adjacent connections) between stacked dies or between die…
pitting corrosion critical pitting temperature prediction, pitting corrosion critical, corrosion critical pitting, critical pitting temperature, pitting temperature prediction
Pitting Corrosion Critical Pitting Temperature Prediction with Machine Learning Introduction & Motivation Pitting Corrosion Critical Pitting Temperature Prediction with Machine…
nlp
Pivot translation is translation that uses an intermediate language between source and target when direct data is limited - The source is translated to a pivot language and then…
multimodal ai
Pivotal Tuning is a subject-specific GAN adaptation method that fine-tunes generator weights around an inverted pivot code - It improves reconstruction accuracy for challenging…
generative models
Pix2Pix is a conditional generative adversarial network (cGAN) framework for paired image-to-image translation that learns a mapping from an input image domain to an output image…
Pix2Pix Conditional Image Translation Introduction & Motivation Pix2Pix Conditional Image Translation addresses a central problem in generative generation…
generative models
Pixel space upscaling is the resolution enhancement performed directly on decoded RGB images using super-resolution or restoration models - it is commonly used as a final pass…
route, algorithm, fundamentals, netlisting, legalization
Place and Route Algorithm Fundamentals is the computational methods for positioning logic gates (placement) and establishing connections between them (routing) — crucial…
design
Place and route (P&R) is the physical-design step that takes the gate-level netlist from synthesis and gives it a concrete form on the die: it decides where every standard cell…
placement routing, pnr flow, apr
Place and Route (PnR) — the automated process of positioning millions to billions of standard cells and connecting them with metal wires to create the physical chip layout.…
place and route convergence and runtime, place route convergence, route convergence runtime, place route, route convergence, convergence runtime
Place and Route Convergence and Runtime Introduction & Motivation Place and Route Convergence and Runtime addresses a central problem in design process control…
standard cell placement, global routing detail routing, timing driven placement, congestion optimization
Place-and-Route (PnR) is the core physical design EDA flow that takes a gate-level netlist and transforms it into a manufacturable chip layout — automatically placing millions…
standard cell placement, global detailed routing, congestion optimization, pnr flow digital
Place and Route (PnR) is the central physical implementation step that transforms a synthesized gate-level netlist into a manufacturable chip layout — placing millions to billions…
place and route timing convergence prediction, place route timing, route timing convergence, timing convergence prediction, place route, route timing, timing convergence
Place and Route Timing Convergence Prediction with Machine Learning Introduction & Motivation Place and Route Timing Convergence Prediction with Machine Learning addresses…
robotics
Place recognition is the task of identifying previously seen locations from current sensor observations using compact visual or geometric descriptors - it is a key module…
pnr, layout
Place and route (P&R) is the physical-design step that takes the gate-level netlist from synthesis and gives it a concrete form on the die: it decides where every standard cell…
manufacturing
Placement accuracy is the degree to which actual component placement position matches intended PCB pad coordinates - it is critical for fine-pitch yield, hidden-joint quality…
placement optimization via reinforcement learning, placement optimization via, optimization via reinforcement, via reinforcement learning, placement optimization, optimization via
Placement Optimization via Reinforcement Learning Introduction & Motivation Placement Optimization via Reinforcement Learning addresses a central problem in design-automation…
apr, global routing, detailed routing, cell placement, legalization, signoff routing
Automated Placement and Routing (APR) is the algorithmic placement of cells into rows and routing of interconnects on metal layers — minimizing wire length, meeting timing…
pick and place, cph throughput
Placement speed is the component placement throughput rate of a pick-and-place system, often expressed as components per hour - it drives line capacity but must be balanced…
doe
Plackett-Burman (PB) Design is a two-level fractional factorial screening design with runs (8, 12, 16, 20, ...) — capable of screening up to factors in runs, providing the most…
ai agent
Plan-and-execute agents separate high-level planning from step-by-step execution for complex tasks. Architecture: Planner generates task decomposition and execution order…
ai agents
Plan Generation is the creation of an actionable sequence of steps for achieving a defined goal - It is a core method in modern semiconductor AI-agent planning and control…
new year sf, nye san francisco, new years eve sf, plan trip sf
Plan New Year Trip San Francisco is travel-planning intent focused on New Year events, logistics, budget, and itinerary design for San Francisco - It is a core method in modern…
hoerni 1959 fairchild mesa etch removed from flow, planar transistor 1959 oxide left in place after diffusion, silicon planar 1959 junction never exposed interface traps
Diffuse Both Junctions Under a Continuous Oxide, Mesa Etch Removed From the Flow: The Step That Isn't There Anymore 1. Why the Biggest Change in This Series Is a Step This Series…
hoerni 1959 lateral diffusion insight surface junction, planar transistor 1959 junction under oxide recognition, silicon planar 1959 realization not new fabrication technique
Recognize That the Masking Oxide Already Covered the Junction the Whole Time: The Insight, Not the Material 1. Why the Lateral Diffusion Everyone Already Knew About Was the Whole…
hoerni 1959 contact window margin lateral diffusion design, planar transistor 1959 window inside diffused region oxide intact, silicon planar 1959 reuses photolithography new purpose
Open Small Contact Windows Through the Oxide by Photolithography: A New Reason for an Old Window 1. Why This Window Serves a Completely Different Purpose Than Every Earlier One…
hoerni 1959 undercut margin junction coverage tradeoff, planar transistor 1959 smallest window maximizes protection, silicon planar 1959 isotropic etch contact window only
Etch Only the Contact Windows, Leaving the Field Oxide Intact Everywhere Else: The Same Acid, a Much Smaller Target 1. Why the Old Undercut Math Now Has to Share the Margin…
hoerni 1959 evaporated film step coverage angle, planar transistor 1959 no mesa sidewall metal crack risk, silicon planar 1959 blanket metal flat topology
Deposit Metal Across the Entire Planar Surface: Why Flatness Is a Property Worth Fighting For 1. Why a Step Height Is an Enemy of an Evaporated Film Long Before It Is an Enemy…
hoerni 1959 metal etch undercut gap base emitter short, planar transistor 1959 second mask aluminum interconnect lines, silicon planar 1959 metal patterned not semiconductor
Pattern the Metal Into Interconnect Lines by a Second Photolithographic Mask: The Same Undercut, a New Way to Fail 1. Why the Gap Between Two Contacts Now Carries the Risk…
hoerni 1959 coverage margin pinhole field oxide inspection, planar transistor 1959 verifying founding premise not spec, silicon planar 1959 confirms exposure never happened
Verify the Junction Is Still Oxide-Covered Everywhere Outside the Contact: Testing This Series' Entire Premise 1. Why This Inspection Checks an Idea, Not Just a Dimension This…