Forksheet Transistor Technology

Forksheet transistor technology inserts a shared dielectric wall between the nMOS and pMOS nanosheet stacks of a gate-all-around device, replacing the open gap that separates them in an ordinary nanosheet transistor. The wall lets designers push the two device types closer together than electrostatics alone would allow, and the resulting cell-height reduction is the whole commercial reason to adopt the structure once nanosheet GAA itself is already in production. Everything else in forksheet design — process integration, gate patterning, parasitic capacitance, and yield — follows from the decision to insert that one dielectric feature.

A forksheet is best understood as a nanosheet transistor with a built-in isolation wall rather than as an entirely new device family. The channel stack, the gate-all-around wrapping, and the source/drain epitaxy are essentially the same nanosheet building blocks used in a conventional GAA transistor; the difference is a dielectric spacer, typically silicon nitride or a low-k variant, grown or deposited in the trench between the nMOS and pMOS sheet stacks before the shared gate is formed. This single addition changes the electrical and process story enough to justify calling it a distinct technology.

The dielectric wall allows nMOS-to-pMOS spacing to shrink by roughly 30-40% compared to an open nanosheet gap, because it removes the electrostatic isolation gap that would otherwise be required. In an ordinary nanosheet device, the n-type and p-type stacks must sit far enough apart that their gate-all-around fields do not interfere destructively, typically demanding a spacing of 40-50 nm. With a dielectric wall physically and electrically isolating the two stacks, that spacing can compress toward 25-30 nm, and the freed area translates directly into a smaller standard-cell footprint.

Cell height reduction of 15-20% is the headline metric that makes forksheet adoption worthwhile at a given node. Standard-cell height is set largely by how close the nMOS and pMOS device rows can sit, so shrinking that spacing by tens of nanometers compounds across every cell in a design, and at advanced nodes with cell heights already down to 100-150 nm, a 15-20% reduction is a meaningful density gain without requiring a new lithography generation or a smaller minimum feature size elsewhere in the process.

Forming the dielectric wall requires an additional patterning and fill step inserted before the shared replacement-metal-gate module, and its placement accuracy is unforgiving. The wall trench must be etched precisely between the two sheet stacks after the sacrificial silicon-germanium release, then filled with a conformal dielectric, all before the gate stack is deposited. A misplaced or non-uniform wall either fails to isolate the two device types electrically or intrudes into the channel region, so overlay and etch-depth control on this single added mask carry outsized weight in overall yield.

Choosing the wall's dielectric constant is a direct trade between isolation quality and parasitic capacitance. A higher-k wall material offers stronger electrostatic isolation between the tightly packed nMOS and pMOS stacks, allowing more aggressive spacing, but it also raises the gate-to-drain parasitic capacitance across the wall, which costs switching energy and speed. Low-k dielectrics such as SiOCN or porous variants, targeting a k value near 3.5-4.5 versus silicon nitride's 7, are the common compromise, trading some isolation margin for a lower parasitic penalty.

The forksheet gate is still shared across both nMOS and pMOS in the sense that a single replacement-metal-gate module wraps both stacks, but the wall makes the two work-function regions independently addressable. Because the wall provides a physical boundary, the n-side and p-side metal fills can be patterned and etched back independently within the same gate trench, which actually simplifies work-function-metal patterning compared to an open nanosheet gap where n/p metal boundaries must be defined without any physical guide structure.

Source and drain epitaxy for the two device types must now be sequenced around the wall rather than around an open gap, changing the masking strategy for each epitaxial growth step. The wall physically blocks unwanted lateral epitaxial growth between the nMOS and pMOS regions during selective epitaxial growth, which is actually a process benefit — it suppresses one merged-epitaxy defect mode that open-gap nanosheet devices must control through spacing alone — but it also means the epitaxy masks must align precisely to the wall's position, adding another overlay-sensitive interface to the flow.

Yield impact from the added wall module shows up primarily as a new overlay-sensitive interface rather than as a fundamentally harder unit process. Each of the individual steps — trench etch, dielectric fill, planarization — is a variant of processes already qualified for nanosheet fabrication, but the requirement that the wall land within a few nanometers of its target position, referenced to both the nMOS and pMOS stack edges, adds a new critical dimension to the overlay budget that a fab must characterize and control before forksheet yields catch up to mature nanosheet yields.

Electrostatic simulation shows the wall must be thick enough to suppress cross-talk between the two gate-all-around fields, typically requiring a minimum wall width near 8-12 nm at advanced nodes. Below that thickness, the nMOS and pMOS gate potentials begin to couple capacitively through the wall, degrading the very electrostatic independence the wall was meant to provide; TCAD studies from groups collaborating with imec and IBM have used tools such as Synopsys Sentaurus to map this thickness-versus-coupling relationship across candidate dielectric constants.

Because the wall is a fixed structural feature once formed, any design change to n/p spacing after wall formation is effectively foreclosed, unlike an open-gap nanosheet device where spacing remains a layout-time choice until later in the flow. This makes wall thickness and target spacing a front-loaded, technology-level decision made by process integration teams at foundries such as TSMC, Samsung, GlobalFoundries, and Intel, rather than a per-design layout knob, which in turn means the density benefit of forksheet is baked into the standard-cell library rather than something each design team optimizes individually.

Parasitic capacitance modeling for forksheet standard cells must add a wall-adjacent term that does not exist in open-gap nanosheet models, and getting this term wrong skews both timing and power signoff. The gate-to-drain capacitance contributed by coupling through the dielectric wall depends on wall thickness, dielectric constant, and the overlap length between the gate and the adjacent stack's drain region, and library characterization teams must extract this as a distinct RC corner rather than folding it into the generic nanosheet parasitic model, or downstream static timing analysis will carry a systematic error specific to forksheet cells.

Thermal budget considerations for the dielectric wall fill step interact with the same sacrificial-release and inner-spacer thermal history that governs conventional nanosheet formation. Because the wall is deposited after channel release, any thermal excursion during wall fill or subsequent anneal steps must stay within the budget already set by the released, unsupported nanosheet channels, which are mechanically fragile until the gate stack provides structural support; exceeding roughly 700-800 °C during this window risks channel sag or bow that propagates into threshold-voltage variation.

Overlay budget for the wall etch step is one of the tightest in the entire forksheet flow, typically specified at a 3-sigma tolerance of 2-3 nm relative to both the nMOS and pMOS stack edges. Missing this tolerance by even 1-2 nm shifts the wall off-center, leaving one side of the device with reduced isolation margin and the other with excess capacitance, so fabs qualifying forksheet processes run extensive overlay-correction studies, often achieving final overlay control near 1.5 nm 3-sigma after several process-control iterations across a 300 mm wafer.

Design-technology co-optimization for forksheet standard cells accounts for the fact that the density gain is realized only if the library, the placement tools, and the process are co-designed from the start. A cell library built naively on top of a forksheet process without re-optimizing track height, pin access, and via placement for the tighter n/p spacing will leave much of the theoretical density gain unrealized, since routing congestion and pin-access rules do not automatically shrink just because the transistor spacing did.

Reliability qualification for the forksheet wall interface focuses on the dielectric's long-term integrity under the electric fields present at the gate edges adjacent to the wall. Time-dependent dielectric breakdown testing must now include a wall-specific failure mode, since the wall sits at a high-field region where the gate-all-around field terminates against the isolation structure, and any voids or interface traps introduced during wall fill can nucleate breakdown at fields lower than the bulk gate dielectric would otherwise tolerate.

Forksheet's relationship to the complementary-FET roadmap is complementary rather than competitive: forksheet is generally viewed as a bridge technology between planar nanosheet GAA and fully vertically stacked CFET. Where forksheet places nMOS and pMOS side by side with a dielectric wall between them, CFET stacks the two device types directly on top of each other, eliminating lateral spacing entirely at the cost of a much more complex 3D integration and via scheme; many roadmaps place forksheet at one node and CFET one or two nodes later, treating forksheet as a lower-risk density step before committing to full vertical stacking.

Metrology for forksheet fabrication adds wall-position and wall-thickness measurement to the existing nanosheet critical-dimension suite, typically via a combination of critical-dimension SEM and TEM cross-sections during process development. Because the wall's position relative to both stacks and its thickness both directly set the achieved n/p spacing and the parasitic capacitance penalty, in-line metrology must resolve these dimensions to sub-nanometer precision, which pushes conventional optical scatterometry to its resolution limit and often requires supplementing it with electron-beam-based measurement for process qualification.

Standard-cell height migration from 5-track and 4-track nanosheet libraries to forksheet-enabled libraries typically targets a further half-track or full-track reduction, compounding with earlier buried-power-rail and backside-power-delivery density gains. Because these density levers are additive rather than mutually exclusive, a process node that combines forksheet transistors with backside power delivery can realize a larger cumulative density gain than either technique alone, which is why leading-edge roadmaps increasingly bundle multiple structural innovations into the same node rather than introducing them one at a time.

Power and performance impact of forksheet adoption is a net gain only after the parasitic capacitance penalty from the wall is subtracted from the density and routing benefits. Circuit-level simulation comparing a forksheet standard-cell library against an equivalent open-gap nanosheet library typically shows a modest 3-5% dynamic power increase from wall-adjacent capacitance, more than offset by the 15-20% area reduction and the routing benefits of a shorter cell, so the net figure of merit favors forksheet at the library level even though a single device in isolation carries a small capacitance penalty.

Foundry roadmaps place forksheet introduction near the 2 nm-class node, layered on top of the nanosheet GAA transition already underway, rather than as a standalone technology generation. This sequencing lets process teams isolate the wall-integration risk from the larger GAA transition risk, qualifying nanosheet electrostatics and yield first, then adding the dielectric wall once the underlying stack, release, and gate-formation processes are stable — a staged de-risking approach common across major foundries including TSMC and Samsung.

Design rule complexity for forksheet-enabled processes grows modestly relative to open-gap nanosheet, adding wall-position, wall-thickness, and wall-adjacent spacing rules to the existing nanosheet rule deck rather than replacing large portions of it. This incremental rather than wholesale rule-deck change is one reason foundries favor forksheet as an evolutionary step: EDA vendors including Synopsys and Cadence can extend existing nanosheet design-rule checkers and parasitic extraction tools with the new wall-specific rules rather than building an entirely new physical-verification flow.

Test structures dedicated to forksheet wall characterization are added to the process-development wafer alongside standard nanosheet scribe-line monitors, measuring wall-adjacent leakage and breakdown voltage directly. These structures typically apply a stress voltage of 1.5-3.0 V across the wall interface at elevated temperature to accelerate any latent defect, extracting a time-to-failure distribution that feeds directly into the reliability qualification described earlier; a wall interface that cannot sustain roughly 10 years of projected field life at nominal 0.7-0.9 V operating voltage fails qualification and sends the integration team back to fill-process tuning.

Looking further ahead, forksheet wall materials research is exploring air-gap or ultra-low-k wall variants to push the capacitance penalty toward zero while retaining the isolation and process benefits of a physical wall. An air-gap wall would essentially eliminate the wall's dielectric constant penalty since air has a relative permittivity near 1.0, but forming and sealing a stable air gap within the tight thermal and mechanical constraints of the gate-formation module remains an open process-integration problem being explored by research groups including those at imec and MIT.

Read forksheet transistor technology through a coupled-systems lens, and the single dielectric wall stops looking like a minor structural tweak and starts looking like a technology-level decision that simultaneously sets density, parasitic capacitance, process complexity, thermal budget, and reliability margin. Sizing the wall, choosing its dielectric, sequencing its formation around the fragile released nanosheet channels, and co-optimizing the standard-cell library around the resulting spacing are not separable engineering tasks — they are one integrated decision that foundries make once, early, and that every downstream cell, timing corner, and yield model then inherits.

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## Appendix

This appendix is not part of the golden section above.