6T SRAM Bit-Cell Stability Simulator

Set a bit-cell operating point — supply, threshold, cell ratio, pull-up ratio, mismatch and array size — then run it: the simulation executes on the ChipFoundryServices distributed compute pool. It solves the two cross-coupled inverters node-by-node to trace the butterfly curve, extracts the hold and read Static Noise Margin from the largest nested square (Seevinck 45° method), sweeps the word-line to find the write margin, and rolls a statistical local-Vth-mismatch model up to the array Vmin — the lowest supply at which the worst cell in a multi-megabit array still holds its bit. Read stability and writeability pull in opposite directions, and on-die cache is often what sets the floor voltage of an AI accelerator. Reduced-order educational model. See also the transistor I-V, thermal, interconnect RC, die-yield, CMP planarization and lithography simulators and the compute-pool status.

HD 6T (foundry) HP 6T (logic) Low-Vdd cache
Butterfly curve — the two cross-coupled inverter VTCs; SNM is the side of the largest square nested in a lobe. Read (dashed) collapses the eye vs. hold (solid)
Left: read SNM vs cell ratio (bigger pull-down → more stable). Right: write margin vs pull-up ratio (weaker pull-up → easier write). Markers are your cell
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/sram \
  -H "Content-Type: application/json" \
  -d '{"vdd":0.80,"vtn":0.30,"vtp_mag":0.30,"cell_ratio":1.5,
       "pull_up_ratio":1.0,"vth_sigma_mv":30,"array_mbit":32}'
Returns JSON with outputs (snm_hold_mv, snm_read_mv, write_margin_mv, trip_point_v, snm_read_worstcase_mv, sigma_target, snm_read_sigma_mv, vmin_v, read_snm_ratio_percent, writable, verdict), the full profile (101-point vtc_hold and vtc_read butterfly curves, 45-point snm_vs_cell_ratio and wwm_vs_pullup_ratio sweeps, trip_point_v), the serving node, and compute_ms.