Map a Transformer matrix multiply — [M×K]·[K×N] — onto a fixed R×C grid of multiply-accumulate PEs (a TPU MXU, a GPU tensor core, an edge NPU), then run it: the simulation executes on the ChipFoundryServices distributed compute pool. It tiles the GEMM onto the array, computes spatial efficiency (edge-tile under-fill) and temporal efficiency (systolic fill/drain amortized over the token stream) to get PE utilization, builds the roofline — arithmetic intensity vs attainable TOPS and the memory/compute ridge point — checks whether a tile's working set fits on-chip SRAM, and rolls energy up to TOPS/W. Compute and HBM bandwidth pull in opposite directions, and PE utilization is usually what separates a datasheet peak from real throughput. Reduced-order educational model. See also the transistor I-V, thermal, interconnect RC, die-yield, 6T SRAM, CMP planarization and lithography simulators and the compute-pool status.
curl -X POST https://www.chipfoundryservices.com/edge/systolic \
-H "Content-Type: application/json" \
-d '{"rows":128,"cols":128,"freq_ghz":1.0,"precision_bits":8,
"hbm_bw_gbs":1600,"sram_mb":24,"mac_pj":0.20,
"gemm_m":2048,"gemm_k":8192,"gemm_n":8192,"dataflow":"ws"}'
Returns JSON with outputs (peak_tops, achieved_tops, pe_utilization_percent,
map_efficiency_percent, temporal_efficiency_percent, arithmetic_intensity, ridge_point_flop_byte,
bottleneck, latency_ms, compute_time_ms, memory_time_ms, hbm_traffic_gb, tiles_k, tiles_n,
tile_working_set_mb, sram_fits, tops_per_watt, power_w, energy_per_inference_mj, verdict), the full
profile (48-point roofline and util_vs_dim sweeps, plus
op_ai, op_tops, ridge_ai, map_eff,
temporal_eff), the serving node, and compute_ms. Accepts
dataflow (ws/os) and endpoint aliases /edge/mxu,
/edge/pe, /edge/gemm, /edge/accelerator.