3,533 technical terms and definitions
ml chip floorplan, automated macro placement, neural network floorplan optimization, reinforcement learning floorplanning
AI-Driven Floorplanning is the automated placement of large blocks and macros on chip floorplan using reinforcement learning and graph neural networks — where RL agents learn…
inference accelerator, inference asic, production ai serving chip
AI inference chip definition and engineering boundary. is hardware optimized to execute trained neural networks under production latency, throughput, energy, and cost constraints.…
aims, lithography
AIMS (Aerial Image Measurement System) is a dedicated metrology tool that emulates the optical conditions of a lithographic scanner to image mask features — reproducing the exact…
metrology
Air bearing table is an ultra-stable measurement platform that floats on a thin film of compressed air — providing friction-free, vibration-isolated support for sensitive…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, atomic layer deposition, ald, ald (atomic layer deposition), atomic layer deposition process, thermal ald, plasma-enhanced ald, peald, spatial ald, thin film ald
Atomic layer deposition is a vapor-phase thin-film deposition technique that builds material one atomic layer at a time through sequential, self-limiting chemical reactions…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald barrier, tantalum nitride barrier, tan ald, diffusion barrier interconnect, copper barrier layer, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald cobalt, cobalt atomic layer deposition, cobalt seed layer, cobalt liner, co ald interconnect, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald cycle, atomic layer deposition cycle, ald half cycle, ald pulse purge cycle, ald cycle timing, ald saturation curve, precursor pulse purge, ald exposure dose
An atomic layer deposition (ALD) cycle is a deliberately separated sequence of surface reactions: precursor A exposure, purge or evacuation, reactant B exposure, and a second…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ald precursor chemistry, atomic layer deposition mechanism, ald nucleation, ald self limiting reaction, thermal ald plasma ald, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
atomic layer deposition, ald, ald basics, atomic layer deposition process, thin film deposition ald, high conformality ald, ald cycle
Atomic layer deposition is a vapor-phase thin-film deposition technique that builds material one atomic layer at a time through sequential, self-limiting chemical reactions…
ald kinetics, atomic layer deposition kinetics, ald growth per cycle, ALD process optimization, atomic layer deposition chemistry, ALD precursor, ALD window, ald
Atomic Layer Deposition is the vapor-phase thin film synthesis technique based on sequential, self-limiting gas-surface chemical reactions that achieves digital monolayer…
overlay metrology 3d, alignment mark design, ir alignment through silicon, alignment error budget
Alignment Accuracy Requirements in 3D integration are the stringent specifications for positioning dies or wafers relative to each other — typically ±0.5-2μm for hybrid bonding…
lithography
Alignment marks are dedicated reference patterns etched or built onto the wafer whose sole purpose is to give every subsequent lithography step a fixed, measurable coordinate…
alloy junction 1952 crystal integrity device fabrication, thermal stress induced dislocation cracking, four point probe resistivity profile ingot
Cool and Inspect the Crystal: Where Step Three's Tolerance Band Gets Measured, Not Assumed Step three managed a drift it could only anticipate; this step is the first point in…
alloy junction 1952 support thin germanium piece assembly, flexural rigidity thin plate deflection wafer, fixture contact stress concentration fracture
Load the Positioning Fixture: Where Step Six's Thickness Choice Becomes a Handling Risk Step six's thickness choice was framed as a trade between wafer count and fragility — more…
alloy junction 1952 remove surface material bridging junction boundaries, parasitic surface bridge parallel resistance junction, restore reverse junction resistance post alloy etch
Perform Post-Alloy Etching: Breaking a Parasitic Bridge, Not Cleaning a Surface It would be easy to mistake this step for Step 8's cleanup etch happening a second time, later…
alloy junction 1952 prevent contamination from tab or attachment materials, galvanic couple nickel germanium etch bath, faraday law galvanic etch depth contribution
Protect the Base Attachment During Etching: A Second Metal Changes the Chemistry Step 30's etch rate law, , assumed a single material sitting in the bath: germanium, dissolving…
alloy junction 1952 multi cycle fresh water rinse after etching, diffusion limited clearance of trapped rinse contaminant, geometric decay residual contamination rinse cycles
Rinse and Dry Thoroughly: Why "Thoroughly" Means Repeated, Not Longer Step 9's rinse, back in Phase 1, was clearing loose particulate off a bare slice with no electrical stakes…
alloy junction 1952 cut thin pieces single crystal, alloy junction 1952 kerf loss wafer count, slice thickness base width upper bound
Slice the Germanium: Fixing the One Number Nothing Downstream Can Ever Exceed Unlike a cut through a grown-junction ingot, nothing about where or how this crystal gets sliced…
alloy junction 1952 thickness usable area before pellet placement, usable area map exclusion zone wafer, placement margin pellet footprint tolerance
Verify Finished Slice Dimensions: Closing Phase One With One Gate, Not Four Separate Ones Four separate steps have each quietly set their own requirement on this wafer — step…
alloy junction 1952 establish intimate metal semiconductor contact, capillary viscous spreading time constant, young laplace pressure trapped void wetting
Wet the Germanium Faces: Reaching Equilibrium Isn't Instant Step nine established the equilibrium condition wetting needs — a clean surface the molten metal would eventually…
alternating psm, altpsm, lithography
Alternating Phase-Shift Mask (AltPSM) is an advanced photomask technology where adjacent clear features transmit light with opposite phases (0° and 180°), creating destructive…
axi bus, on chip interconnect, ahb apb
AMBA / AXI Bus — ARM's standardized on-chip interconnect protocol family that defines how IP blocks (CPUs, GPUs, DMAs, peripherals) communicate inside an SoC. AMBA Protocol Family…
AMD Ryzen, AMD EPYC, AMD Instinct, Zen processor, AMD chiplet
AMD processor. covers AMD’s fabless portfolio of Ryzen client CPUs, EPYC server CPUs, Radeon graphics, Instinct AI and HPC accelerators, adaptive-computing products…
amorphous oxide semiconductor tft stability prediction, amorphous oxide semiconductor, oxide semiconductor tft, semiconductor tft stability, amorphous oxide
Amorphous Oxide Semiconductor TFT Stability Prediction with Machine Learning Introduction & Motivation Amorphous Oxide Semiconductor TFT Stability Prediction with Machine Learning…
cvd amorphous silicon, hydrogenated amorphous silicon, a-si deposition, amorphous silicon nucleation, amorphous silicon anneal, amorphous silicon hydrogen, amorphous silicon defects, amorphous silicon bandgap, amorphous silicon passivation
Amorphous silicon is a metastable silicon network whose useful behavior comes from controlling disorder, dangling bonds, hydrogen, interfaces, and thermal history. It has no…
amorphous silicon deposition uniformity prediction machine learning, amorphous silicon, deposition uniformity prediction, pecvd, amorphous silicon deposition
Amorphous Silicon Deposition Uniformity Prediction with Machine Learning Introduction & Motivation Amorphous Silicon Deposition Uniformity Prediction with Machine Learning…
adc dac converter design, analog circuit semiconductor, pll frequency synthesizer, analog ip block
Analog and Mixed-Signal IC Design is the semiconductor discipline that creates circuits processing continuous (analog) signals — amplifiers, data converters (ADC/DAC)…
theta 2theta scan, angular diffraction fingerprint, diffraction based overlay DBO, fixed wavelength measurement, hybrid metrology, specular reflectance, model based parameter extraction
Angle-resolved scatterometry is a variant of optical scatterometry that measures a periodic structure's diffraction signature as a function of incidence angle rather than…
arxps, angle resolved x-ray photoelectron spectroscopy, angle resolved photoelectron spectroscopy, nondestructive xps depth profiling, arxps depth profile, arxps semiconductor
Angle-resolved X-ray photoelectron spectroscopy changes the electron takeoff geometry to obtain several differently depth-weighted views of the same near-surface chemistry. Normal…
acf, packaging
Anisotropic conductive film is the adhesive film containing conductive particles that create electrical conduction only in the thickness direction under pressure and heat - it…
process
Anisotropic etching is the etch process where material removal rate depends strongly on crystallographic direction or sidewall orientation - it enables geometric control that…
anneal ramp rate wafer warpage prediction machine learning, anneal ramp, rate wafer warpage, rtp, anneal ramp rate wafer warpage prediction, anneal ramp rate, ramp rate wafer
Anneal Ramp Rate Wafer Warpage Prediction with Machine Learning Introduction & Motivation Anneal Ramp Rate Wafer Warpage Prediction with Machine Learning addresses a central…
abf, metrology
ABF (Annular Bright Field) is a STEM imaging mode that collects electrons at small-to-medium scattering angles — providing contrast for both heavy and light elements…
advanced packaging
Anodic Bonding is a wafer-level bonding technique that joins glass to silicon using a combination of elevated temperature and high electric field — driving mobile sodium ions…
outlier detection eda, abnormal pattern identification, design defect detection, statistical anomaly chip
Anomaly Detection in Design is the application of unsupervised and semi-supervised machine learning to identify unusual, unexpected, or potentially problematic patterns in chip…
antenna rule, antenna diode, charge accumulation gate, antenna violation
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
arc bottom arc, bottom arc, organic arc, silicon arc barc, arc lithography
Anti-Reflective Coating (ARC) An anti-reflective coating (ARC) in photolithography is a deliberately engineered optical layer used to reduce reflected exposure energy and…
anti-reflective coating, arc, lithography
Anti-Reflective Coating (ARC) An anti-reflective coating (ARC) in photolithography is a deliberately engineered optical layer used to reduce reflected exposure energy and…
esd protection, static shielding
Electrostatic Discharge (ESD) protection constitutes the dedicated on-chip network of high-current shunting devices engineered to safeguard sensitive gate dielectrics, thin tunnel…
Applied Materials semiconductor equipment, AMAT equipment, Endura PVD, Producer CVD, Reflexion CMP
Applied Materials. is a major semiconductor and display equipment company supplying systems, process modules, services, and technology used to create and inspect material…
selective deposition metal, bottom up metal growth, self aligned metal fill, pattern selective metallization
Area-Selective Metal Deposition is the chemistry selective deposition technique that grows metal only on intended surfaces to reduce patterning steps. What It Covers Core concept…
arf, argon fluoride, lithography
ArF (argon fluoride) excimer lasers produce the 193nm deep-UV light that powers the most advanced DUV lithography systems — the workhorse behind everything from 90nm down…
asic versus fpga, difference between asic and fpga, when to use fpga vs asic, custom chip vs programmable chip
An ASIC and an FPGA solve the same problem — running a custom digital circuit — with opposite tradeoffs between speed and flexibility: an ASIC is a chip permanently hardwired…
euv machine, lithography equipment, scanner
ASML is the sole manufacturer of EUV lithography systems in the world — not the leading supplier, the *only* supplier. Every chip below the 7nm node, from every major foundry on…
euv machine, lithography equipment, scanner
ASML is the sole manufacturer of EUV lithography systems in the world — not the leading supplier, the *only* supplier. Every chip below the 7nm node, from every major foundry on…
why does asml have a monopoly, asml monopoly on euv, why only asml makes euv, asml lithography monopoly, euv scanner monopoly
ASML is the only company on Earth that builds extreme ultraviolet lithography scanners, and that is not an accident of market share the way one company might simply out-compete…
ARDE, aspect ratio dependent etching, rie lag, microloading, etch loading effect, knudsen diffusion etch, plasma etch lag, etch
Aspect-ratio-dependent etching and microloading are fundamental plasma transport phenomena in reactive ion etching where the instantaneous material removal rate diminishes…
production, die attach void, wire bond failure, wire sweep, molding defect, handling damage, packaging equipment health, sunk cost die loss, assembly process control
Assembly yield is the percentage of die that survive the packaging process intact and functional, measuring how well die attach, wire bonding or bumping, and molding preserve…
surface roughness afm, afm surface roughness, roughness metrology, metrology
Atomic force microscopy profiles a surface by rastering a sharp tip on a flexible cantilever and using a feedback-controlled z scanner to follow the tip-sample interaction.…