Darkfield Inspection
metrology
Darkfield Inspection is a semiconductor metrology technique that illuminates wafers at oblique angles and collects only scattered light from defects — blocking the specular…
143 technical terms and definitions
metrology
Darkfield Inspection is a semiconductor metrology technique that illuminates wafers at oblique angles and collects only scattered light from defects — blocking the specular…
input pipeline, prefetching data, data loader, io bound training
ML Data Pipeline is the system that efficiently loads, preprocesses, and batches training data — a bottleneck that can reduce GPU utilization from 100% to < 30% if poorly…
data prefetching accuracy prediction, data prefetching accuracy, prefetching accuracy prediction, data prefetching, prefetching accuracy, accuracy prediction
Data Prefetching Accuracy Prediction with Machine Learning Introduction & Motivation Data Prefetching Accuracy Prediction with Machine Learning addresses a central problem in data…
packaging
Date code is the encoded manufacturing-time identifier printed or marked on packages to indicate production period for traceability - it supports quality control, inventory…
direct current sputtering, dc magnetron sputtering, dc sputter deposition, dc sputtering power, dc sputtering voltage, dc sputtering current, dc sputtering arcing, pulsed dc sputtering, reactive dc sputtering, dc plasma impedance, arc suppression
DC sputtering is the electrical operating regime in which a negative direct-current supply sustains a glow discharge at a conductive cathode target, converting a controlled…
drift transistor 1956 silicon wafer resistivity orientation, double diffused mesa transistor 1956 collector resistivity choice, silicon bandgap starting material silicon mesa drift transistor
Select and Prepare the Starting Silicon Wafer: Choosing the Crystal That Will Carry a Field It Doesn't Yet Have 1. Why Silicon's Resistivity Has to Be Chosen Before Anything Else…
drift transistor 1956 wafer cleaning lapping cmp, double diffused mesa transistor 1956 contamination trap leakage, silicon surface preparation diffusion readiness drift transistor
Surface Clean and Polish the Wafer: Removing Everything a Diffusion Furnace Would Otherwise Copy Into the Crystal 1. Why a Furnace Cannot Be Trusted to Ignore a Dirty Surface…
drift transistor 1956 boron surface doping dose, double diffused mesa transistor 1956 predeposition drive in separation, boron solid solubility surface concentration drift transistor
Base Predeposition: Laying Down the Boron That Will Become a Graded Base, Not Yet a Flat One 1. Why Predeposition Is Deliberately Separated From Drive-In This step introduces…
drift transistor 1956 emitter shallow heavy doping, double diffused mesa transistor 1956 emitter base junction placement, phosphorus emitter diffusion drift field silicon mesa 1956
Emitter Predeposition: A Second Dopant, Opposite Polarity, Placed Inside a Field That Is Already Waiting For It 1. Why the Emitter Must Be Shallower and More Heavily Doped Than…
drift transistor 1956 wafer dicing trench cut, double diffused mesa transistor 1956 dicing grid mesa, die separation yield risk silicon drift transistor 1956
Die Separation: Turning a Wafer Full of Finished Transistors Into Individually Handleable Parts 1. Why Electrical Isolation From Step 9 Did Not Make Physical Separation…
dielectric deposition, high-k dielectrics, ald, pecvd, gap fill, hdpcvd, feature-scale modeling
Semiconductor Manufacturing: Dielectric Deposition Process (DDP) Modeling Overview DDP (Dielectric Deposition Process) refers to the set of techniques used to deposit insulating…
advanced packaging
Debonding is the controlled process of separating a thinned device wafer from its temporary carrier wafer after backside processing is complete — requiring precise management…
wafer debonding methods, thermal debonding, uv debonding laser, debonding force measurement
Wafer Debonding Processes in Semiconductor Manufacturing Wafer debonding is the critical separation technology in temporary bonded wafer processing, enabling ultra-thin device…
dedicated experiment wafer scheduling prediction machine learning, dedicated experiment, wafer scheduling prediction, dedicated experiment wafer scheduling prediction
Dedicated Experiment Wafer Scheduling Prediction with Machine Learning Introduction & Motivation Dedicated Experiment Wafer Scheduling Prediction with Machine Learning addresses…
The Bosch Process: Where Scallops Actually Come From Keyword focus: deep reactive ion etching DRIE Bosch process passivation C4F8 etch SF6 scalloping high aspect ratio silicon HAR…
drie, advanced packaging, bosch process, tsv etch
Through-Silicon Vias are the vertical conductive interconnect pillars that traverse the bulk silicon substrate to establish high-density, low-latency electrical connections…
critical defect density, D0, die yield model, wafer defect map
Defect density. is the number of defects of a defined class per unit inspected area, commonly reported in defects per square centimeter. For yield modeling, the important quantity…
wafer defect mapping, semiconductor metrology defects, yield defect analysis, fab defect analytics
Defect Density Map is the spatial representation of defect concentration across a wafer, lot, or process module used to diagnose yield loss mechanisms, tool issues, contamination…
metrology
Metrology and inspection are the two measurement disciplines that keep a semiconductor fab in control — they are how a foundry knows, wafer by wafer, whether hundreds of process…
wafer inspection, defect review, kla inspection
Defect Inspection — detecting and classifying nanoscale defects on wafers during fabrication to maintain yield, the critical feedback loop that keeps a semiconductor fab running.…
wafer inspection defect review, defect classification fab workflow, inline defect detection, defect disposition yield learning
Defect inspection and review workflow is the inline machinery that turns a raw pattern of light scattered off a wafer into an actual engineering decision about whether that wafer…
wafer inspection techniques, defect classification review, killer defect analysis, yield learning methodology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
metrology
Defect Review is the high-resolution imaging step that follows optical wafer inspection, in which a scanning electron microscope (SEM) navigates to the coordinates of each flagged…
dsa, metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
packaging
Deflashing is the post-molding operation that removes excess compound from parting lines, runners, and non-functional surfaces - it restores package geometry and cleanliness…
cvd, pvd, ald, atomic layer deposition, chemical vapor deposition, sputtering, electrodeposition, copper plating, thin film, superfilling, high k metal gate, thin film deposition, book 6
Deposition & Materials: Atom-by-Atom Precision — Thin-Film Physics, Surface Chemistry & Equipment Moats While lithography patterns the circuit and etch carves the physical…
deposition chamber gas phase reaction kinetics, deposition chamber gas, chamber gas phase, gas phase reaction, phase reaction kinetics, deposition chamber, chamber gas
Deposition Chamber Gas Phase Reaction Kinetics with Machine Learning Introduction & Motivation Deposition Chamber Gas Phase Reaction Kinetics with Machine Learning addresses…
cvd deposition rate, thin film deposition rate, film growth rate, cvd growth rate, deposition rate calculation, deposition rate units, net deposition rate, film growth velocity, deposition rate measurement, cvd
Deposition rate is the net increase of film thickness, mass, or material amount per unit time under a defined process state. It is commonly reported in Å/s, nm/min, µm/h, mass per…
deposition shield lifetime prediction machine learning, deposition shield, lifetime prediction machine, pvd, deposition shield lifetime prediction, deposition shield lifetime
Deposition Shield Lifetime Prediction with Machine Learning Introduction & Motivation Deposition Shield Lifetime Prediction with Machine Learning addresses a central problem…
cvd modeling, film growth model
Deposition Simulation uses computational models to predict thin film growth, enabling process optimization before expensive experimental runs. What Is Deposition Simulation?…
depth of focus, dof, lithography
Depth of focus (DOF) is the range of vertical wafer positions over which the projected image stays sharp enough to print features within spec — and it's locked in a direct…
convergence, sign-off closure, chip closure, physical implementation closure
Design Closure is the iterative process of simultaneously satisfying all physical design constraints — timing, power, area, DRC, LVS, and signal integrity — to reach…
dfd, trace buffer, logic analyzer on chip, silicon debug infrastructure
Design-for-Debug (DfD) Infrastructure is the set of on-chip hardware structures (trace buffers, trigger logic, performance counters, and debug buses) built into a chip to enable…
DFM, DFM rules, yield aware design, lithography friendly design, CMP aware layout
Design for manufacturability. is the practice of shaping a legal circuit layout so it prints, deposits, etches, planarizes, assembles, and operates with more margin across…
lithography aware design, yield enhancement techniques, dfm rules checking, manufacturing hotspot detection
Design for Manufacturability (DFM) is the set of design practices, rules, and optimizations that improve the probability of manufacturing defect-free chips by accounting…
lithography aware design, chemical mechanical polishing, yield optimization layout, process variation compensation
Design for Manufacturing DFM — Design for manufacturing (DFM) encompasses layout optimization techniques that improve fabrication yield and process robustness by accounting…
chip hierarchy, block level design, top level integration
Hierarchical Design Methodology is the divide-and-conquer approach to chip design where a complex SoC is decomposed into independently designable blocks (IP cores, subsystems…
process
Design of Experiments (DOE) in semiconductor manufacturing is a systematic, statistical methodology for varying process parameters to determine their effects on output quality…
multi objective optimization chip, constrained optimization eda, gradient free optimization, evolutionary strategies design
Design Optimization Algorithms are the mathematical and computational methods for systematically searching chip design parameter spaces to find configurations that maximize…
lvs layout versus schematic, physical verification eda, foundry rule deck, drc violation
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
drc waiver, violation waiver, foundry waiver
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
automated ppa optimization, multi objective chip optimization, pareto optimal design, ml guided design search
ML-Driven Design Space Exploration is the automated search through billions of design configurations to find Pareto-optimal solutions that balance power, performance, and area…
metrology
Detection Limit (LOD — Limit of Detection) is the lowest quantity or concentration of an analyte that can be reliably distinguished from zero — the minimum detectable signal that…
photoresist develop, photoresist development, tmah development, resist dissolution kinetics, alkaline developer, pattern development, dissolution rate, lithography
Photoresist development is the chemical process that selectively dissolves and removes either exposed or unexposed polymer regions from a photoresist film in an aqueous alkaline…
device physics math, semiconductor device physics, TCAD modeling, drift diffusion, poisson equation, mosfet physics, quantum effects
Device Physics & Mathematical Modeling 1. Fundamental Mathematical Structure Semiconductor modeling is built on coupled nonlinear partial differential equations spanning multiple…
tcad, device physics, semiconductor device physics, band theory, drift diffusion, poisson equation, boltzmann transport, carrier transport, mobility models, recombination models, process tcad
Device Physics, TCAD, and Mathematical Modeling Every transistor is governed by the same physics — the drift and diffusion of charge carriers through a doped crystal under…
advanced packaging
Device Wafer is the silicon wafer containing the fabricated integrated circuits (transistors, interconnects, memory cells) that will become the final semiconductor product…
semiconductor devices, semiconductor device, mosfet, cmos, transistor types, subthreshold swing, leakage current, gate all around, nanosheet, cfet, hemt, igbt, sic mosfet, gan hemt, power devices, memory cell, steep slope devices
A semiconductor device is a structure that exploits the controllable conductivity of a semiconductor to do one useful job: switch, amplify, rectify, store charge, or convert…
dfm lithography hotspot prediction, dfm lithography hotspot, lithography hotspot prediction, dfm lithography, lithography hotspot, hotspot prediction
DFM Lithography Hotspot Prediction with Machine Learning Introduction & Motivation DFM Lithography Hotspot Prediction with Machine Learning addresses a central problem…
litho friendly design, critical area analysis, caa, dfm litho, lithography friendly design rules
Design for Manufacturability (DFM) — Lithography Rules is the set of design guidelines that extend beyond minimum DRC (Design Rule Check) rules to ensure that circuit layout…