254 technical terms and definitions
bardeen brattain 1947 step 2 cut germanium body, cut small block or disc germanium, saw damage machining allowance germanium body, create the semiconductor body point contact
Cut a Small Block or Disc: The First Operation That Can Destroy What Step 1 Selected For Step 1 accepted a germanium sample on the strength of a property that lives in the bulk…
bardeen brattain 1947 step 7 reetch upper face, re-etch the upper face germanium contamination, stray metal contamination threshold surface states, conditional step line of sight deposition germanium
Re-Etch the Upper Face: The First Step in This Sequence That Might Not Run at All Every step so far has run unconditionally — the sample selected in Step 1 either passed its…
p well process, single-well cmos, cmos well architecture, semiconductor process wells, twin-well cmos comparison
P-well CMOS process builds NMOS transistors inside a p-type well diffused into an n-type starting substrate, while PMOS transistors sit directly in the surrounding n-substrate…
packaging, can you package, assembly, package my chips
Packaging is the step that turns a finished, fragile silicon die into a usable component: it protects the chip mechanically and environmentally, connects its microscopic on-chip…
packaging
Package body size is the length and width dimensions of the package body excluding lead extensions or terminal protrusions - it defines board footprint density and mechanical…
packaging
Package dimensions is the measured geometric attributes of semiconductor packages including body size, thickness, lead features, and offsets - they determine mechanical fit…
packaging
Package height is the overall vertical dimension of a semiconductor package from board-contact plane to top surface - it determines z-axis clearance, stacking compatibility…
packaging
Package marking is the process of permanently printing or engraving identification information onto the surface of a semiconductor package. This marking provides essential…
packaging
Package molding is the semiconductor assembly process that encapsulates dies and interconnect structures in protective molding compound - it provides mechanical protection…
pop packaging, pop memory, stacked package, memory logic pop, 3d package stack
Package-on-Package (PoP) is the 3D packaging configuration that stacks a memory package (LPDDR DRAM) directly on top of a processor package (SoC/AP), connecting them through…
packaging
Package outline drawings is the technical drawings that specify external package geometry, dimensions, tolerances, and reference features - they are the authoritative interface…
packaging
Package warpage from molding is the out-of-plane deformation of packaged devices caused by residual stress and thermal mismatch generated during molding and cure - it affects…
advanced chip packaging, semiconductor package landscape
For most of computing history, more performance meant more transistors on one monolithic die. As that path slows, the industry increasingly gains performance through advanced…
ABF, Ajinomoto build-up film, glass core, fine line, HDI
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
packaging, large-scale, processing, throughput, cost, RDL, singulation
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
panel-level packaging warpage prediction, panel-level packaging warpage, packaging warpage prediction, panel-level packaging, packaging warpage, warpage prediction
Panel-Level Packaging Warpage Prediction with Machine Learning Introduction & Motivation Panel-Level Packaging Warpage Prediction with Machine Learning addresses a central problem…
panel level packaging warpage prediction with machine learning, panel level packaging warpage prediction machine learning, panel level, packaging warpage prediction, cte rdl
Panel-Level Packaging Warpage Prediction with Machine Learning Introduction & Motivation Panel-Level Packaging Warpage Prediction with Machine Learning addresses a central problem…
metrology
Parametric testing measures key electrical parameters of transistors and structures on the wafer to monitor process health and detect process shifts. Purpose: Verify that…
parametric test structure, wafer parametric test, parametric electrical test, pcm parametric test
Parametric testing is the electrical checkpoint that stands between a finished process flow and a wafer being released to the next stage, using small dedicated test structures…
optimization
Pareto Optimization in semiconductor manufacturing is the identification of the set of non-dominated solutions (Pareto front) — where no solution can improve one objective without…
process integration, dual-damascene, via-first, trench-first, via lithography, aspect ratio, trench etch, BEOL patterning, resist defects
Partial via-first is a hybrid dual-damascene integration sequence that starts etching the via before the trench is even patterned, but deliberately stops that via etch partway…
metrology
Particle Counting on Surfaces is the automated, full-wafer laser scanning inspection technique that detects, localizes, and sizes individual particle defects on bare silicon wafer…
metrology
Particle Size Distribution (PSD) is the statistical characterization of particle contamination that reports defect counts binned by size rather than as a single total number…
pso chip design, swarm intelligence routing, pso parameter tuning, velocity position update pso
Particle Swarm Optimization (PSO) is the swarm intelligence algorithm inspired by bird flocking and fish schooling that optimizes chip design parameters by maintaining…
chip passivation, final coating, nitride passivation
Passivation Layer — the final protective coating deposited over the completed chip to shield it from moisture, contamination, mechanical damage, and corrosion during packaging…
chip passivation, final passivation semiconductor, sin passivation, polyimide passivation
Passivation Layer Deposition is the final protective thin-film coating applied over the completed integrated circuit — typically a bilayer of silicon nitride (SiN) over silicon…
overlay, registration, alignment, wafer alignment, die placement, pattern transfer, lithography alignment, overlay error, placement accuracy
Overlay is the layer-to-layer alignment accuracy of a chip — how precisely the pattern printed at one lithography step lands on the patterns already on the wafer. A chip is built…
patterned wafer defect classification drift prediction machine learning, patterned wafer, defect classification drift, adc, patterned wafer defect, wafer defect
Patterned Wafer Defect Classification Drift Prediction with Machine Learning Introduction & Motivation Patterned Wafer Defect Classification Drift Prediction with Machine Learning…
patterned wafer effect holistic prediction, patterned wafer effect, wafer effect holistic, effect holistic prediction, patterned wafer, wafer effect, effect holistic
Patterned Wafer Effect Holistic Prediction with Machine Learning Introduction & Motivation Patterned Wafer Effect Holistic Prediction with Machine Learning addresses a central…
metrology
Patterned Wafer Inspection is the automated optical or e-beam scanning of wafers after circuit patterns have been printed and etched, using die-to-die or die-to-database image…
principal component analysis, dimensionality reduction, eigenvalue, eigendecomposition, variance, semiconductor pca, fdc
Principal Component Analysis (PCA) in Semiconductor Manufacturing: Mathematical Foundations 1. Introduction and Motivation Semiconductor manufacturing is one of the most complex…
pcm, process control monitor, metrology
PCM (Process Control Monitor) uses dedicated test structures or wafers to monitor the manufacturing process independently from product wafers, ensuring process stability…
packaging
Peak reflow temperature is the maximum temperature reached by the assembly during reflow, set high enough for complete solder wetting but low enough to protect materials - it is…
plasma-enhanced deposition, PECVD process, silicon nitride PECVD, SiN deposition
Plasma-enhanced chemical vapor deposition has evolved from a niche laboratory technique into the workhorse thin-film deposition technology for advanced semiconductor…
plasma deposition, pecvd film
Plasma-Enhanced CVD (PECVD) is a thin film deposition technique that uses plasma to activate chemical reactions at lower temperatures than thermal CVD — enabling dielectric…
pecvd (plasma-enhanced cvd), plasma-enhanced cvd, cvd, plasma enhanced chemical vapor deposition, pecvd chamber, plasma deposition, low temperature cvd, rf pecvd
PECVD trades substrate heat for plasma energy: electron-driven dissociation creates reactive radicals at low wafer temperature, while sheath-accelerated ions, hydrogen…
pecvd silicon nitride oxide, pecvd film stress control, pecvd low temperature deposition, pecvd dielectric interlayer
Plasma-Enhanced Chemical Vapor Deposition (PECVD) is a thin film deposition technique that uses radio-frequency plasma to activate gas-phase precursors at temperatures 200-400°C…
lithography, standoff distance, pellicle frame, transmission loss, EUV pellicle, carbon nanotube membrane, DUV pellicle, haze degradation, contamination protection
Pellicle mounting attaches a thin, transparent membrane over a mask's patterned surface, held a precisely-defined standoff distance away — not touching the pattern itself — so…
packaging, board layer count, escape routing, ball map planning, PCB cost reduction, depopulated array, moderate pin count package, assembly process window, edge ball placement
Peripheral BGA is a ball-array layout that concentrates solder balls in the outer rows near a package's edges while leaving the center partially or fully empty — deliberately…
advanced packaging
Permanent bonding after thinning is the final joining process that permanently attaches thinned wafers or dies to target substrates for electrical, thermal, and mechanical…
phase-shift mask, psm, lithography
Phase-Shift Mask (PSM) is a photolithography reticle technology that uses transparent regions of different optical path lengths to create destructive interference at feature…
raman phonon analysis, phonon mode assignment, phonon dispersion analysis, raman mode symmetry, semiconductor phonon modes, phonon spectroscopy metrology
Phonon mode analysis turns peaks into a model of how atoms move, how crystal symmetry constrains that motion, and how the lattice responds to temperature, stress, composition…
oxide masking 1957 silicon dioxide diffusion barrier, photolithography 1957 bell labs andrus bond dofl lathrop, thermal oxidation consumes silicon interface 1957 oxide mask
Grow the Thermal Oxide Layer: Turning Silicon's Own Native Chemistry Into a Diffusion Barrier 1. Why Silicon Dioxide Can Stop a Dopant That Silicon Cannot This step heats…
oxide masking 1957 interference color ellipsometry measurement, photolithography 1957 oxide uniformity wafer edge failure, deal grove oxidation law oxide mask verification 1957
Verify Oxide Thickness and Uniformity: Measuring a Barrier Before Trusting It to Hold 1. Why a Barrier Has to Be Measured Before It Is Believed This step takes the oxide Step 1…
oxide masking 1957 spin coating resist thickness speed, photolithography 1957 kodak photoresist printing industry origin, resist edge bead spin coat uniformity 1957 oxide mask
Apply the Photoresist Coating: Borrowing a Printing-Industry Chemistry and Asking It to Hold a Micron 1. Why a Film From the Printing Trade Had to Learn a New Tolerance This step…
oxide masking 1957 solvent removal resist adhesion bake, photolithography 1957 resist tacky mask contamination risk, arrhenius solvent loss soft bake window 1957 oxide mask
Soft-Bake the Photoresist: Driving Off Solvent Without Driving Off Sensitivity 1. Why Two Different Reactions Share the Same Oven and Disagree About the Temperature This step…
oxide masking 1957 overlay registration error budget, photolithography 1957 lathrop nall dofl microscope alignment, systematic misalignment whole wafer loss 1957 oxide mask
Align the Photomask to the Wafer: The Step Where Geometry Becomes a Registration Problem 1. Why Alignment Is Easy Once and Hard Every Time After This step brings a photomask…
oxide masking 1957 exposure dose resist contrast gamma, photolithography 1957 diffraction near contact feature limit, light replaces physical tooling geometry 1957 oxide mask
Expose the Photoresist Through the Mask: Where a Pattern Stops Being Glass and Becomes Chemistry 1. Why a Blurred Optical Edge Can Still Produce a Sharp Chemical One This step…
oxide masking 1957 developer selectivity dissolution rate, photolithography 1957 residual resist skin blocked window, latent image becomes topography develop 1957 oxide mask
Develop the Exposed Photoresist: Turning a Latent Chemical Difference Into an Actual Hole 1. Why the Pattern Has Been Invisible Until This Moment This step immerses the wafer in…
oxide masking 1957 resist adhesion flow temperature optimum, photolithography 1957 hf undercut resist edge lifting, competing arrhenius rates hard bake window 1957 oxide mask
Hard-Bake the Developed Resist: Toughening a Pattern for the Acid That Comes Next 1. Why the Safer-Looking Temperature Is Not Automatically the Right One This step returns…