3,538 technical terms and definitions
rayleigh resolution limit feature size critical dimension, excimer laser mercury xenon lamp coherent light
A photolithography light source is the illumination system that generates the UV or EUV light used to project a chip's circuit pattern onto the photoresist-coated wafer — and…
photolithography step 23 multiple patterning at scale, multiple patterning at scale
Multiple Patterning at Scale: Step 23 Patterning 3+ times to print sub-wavelength features, complexity and yield tradeoffs Step 23 advances photolithography by addressing key…
photolithography step 10 optical proximity correction, optical proximity correction opc
Optical Proximity Correction (OPC): Step 10 Mask compensation for diffraction, off-axis illumination, resist bias correction Step 10 advances photolithography by adjusting mask…
scanner alignment, registration error, overlay budget, layer registration lithography
Overlay metrology measures the in-plane registration vector between a newly patterned lithography layer and a reference layer already on the wafer. A tool observes dedicated…
photolithography step 20 pattern transfer and etch, pattern transfer and etch
Pattern Transfer and Etch: Step 20 Reactive ion etching (RIE), resist stripping, multilayer etch sequences Step 20 advances photolithography by addressing key mechanisms affecting…
photolithography step 24 pellicle masks and protection, pellicle masks and protection
Pellicle Masks and Protection: Step 24 Pellicle protection from particles, thermal management, pellicle defect control Step 24 advances photolithography by addressing key…
photolithography step 11 phase shifting masks, phase shifting masks psm
Phase-Shifting Masks (PSM): Step 11 Attenuated and alternating phase masks, contrast enhancement, PSM design Step 11 advances photolithography by exploiting wave interference…
photolithography step 25 photolithography manufacturing and yield, photolithography manufacturing and yield
Photolithography Manufacturing and Yield: Step 25 Production throughput, defect sources, yield optimization, cost-per-chip Step 25 advances photolithography by addressing key…
photolithography step 12 polarization effects and control, polarization effects and control
Polarization Effects and Control: Step 12 Radial/azimuthal polarization, vector diffraction, polarization-resolved imaging This step advances photolithography by addressing…
photolithography step 19 resist outgassing and line collapse, resist outgassing and line collapse
Resist Outgassing and Line Collapse: Step 19 Resist pattern collapse, outgassing, aspect-ratio-dependent etching (ARDE), sidewall support Step 19 advances photolithography…
photolithography step 22 resist trimming and refinement, resist trimming and refinement
Resist Trimming and Refinement: Step 22 Trim process optimization, sidewall smoothing, CD tightening, pattern refinement Step 22 advances photolithography by addressing key…
photolithography step 9 resolution limits diffraction, resolution limits and diffraction
Resolution Limits and Diffraction: Step 9 The physics barrier to pattern fineness and techniques to overcome it Step 9 explores the diffraction limit — why we cannot print…
photolithography step 17 self-aligned double patterning, self aligned double patterning
Self-Aligned Double Patterning: Step 17 Mandrel creation, spacer deposition, line doubling without trim alignment This step advances photolithography by addressing [topic]. Step…
photolithography stepper alignment overlay prediction, photolithography stepper alignment, stepper alignment overlay, alignment overlay prediction, stepper alignment
Photolithography Stepper Alignment Overlay Prediction with Machine Learning Introduction & Motivation Photolithography Stepper Alignment Overlay Prediction with Machine Learning…
photoluminescence spectroscopy, pl spectroscopy, semiconductor photoluminescence, band edge emission
Photoluminescence spectroscopy asks what happens after a semiconductor absorbs light energetic enough to create excited carriers. Some electrons and holes recombine radiatively…
pl mapping, wafer photoluminescence mapping, semiconductor pl imaging, photoluminescence uniformity map
Photoluminescence spectroscopy asks what happens after a semiconductor absorbs light energetic enough to create excited carriers. Some electrons and holes recombine radiatively…
reticle, mask blank, mask fabrication, e-beam mask writing, phase shift mask
Photomask (reticle): the master pattern for a chip layer. A photomask controls where exposure light reaches the wafer. Projection optics form a smaller image in photoresist…
photomask fabrication, phase-shift mask, psm, reticle manufacturing, mask blank defect, ebeam mask writing
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
mask blank defect, mask pattern writing, phase shift mask, mask repair
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
EUV mask, mask blank, absorber, reticle fabrication
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
lithography
Photon shot noise is the fundamental statistical variation in the number of photons arriving at any given point on the wafer during lithographic exposure. Since photons are…
lithography
A photon sieve is an alternative optical element for EUV lithography that uses a pattern of precisely placed pinholes in an opaque membrane to focus light through diffraction…
photonic integrated circuit, silicon photonics design, ring resonator optical, mach zehnder modulator
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
mach zehnder modulator mlp, optical matrix vector multiply, silicon photonic chip ai, optical memory bottleneck
Photonic Computing: Optical Matrix-Vector Multiplication via Mach-Zehnder Interferometer Mesh — exploits wavelength-division multiplexing and optical parallelism to achieve…
PIC, fabrication, waveguide
Photonic Integrated Circuit PIC Fabrication is an advanced manufacturing process technology that integrates multiple optical components (waveguides, modulators, switches…
silicon photonics fabrication, optical waveguide technology, photonic chip manufacturing, integrated optical components
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics manufacturing, pic foundry, optical waveguide semiconductor, photonic chip process
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics, optical transceiver, co packaged optics cpo, photonic semiconductor
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
silicon photonics manufacturing, optical transceiver chip, photonic waveguide fabrication, pic semiconductor process
Silicon photonics and optical I/O technologies integrate high-density optical waveguides, electro-optic modulators, photodetectors, and heterogeneous laser sources onto standard…
lithography, chemically amplified resist, photoresist chemistry, euv resist
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist, euv photoresist, resist resolution limit, metal oxide resist
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
positive negative photoresist, chemically amplified resist, euv photoresist development, photoresist processing lithography
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist, euv photoresist, resist development process, dry resist metal oxide
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
euv photoresist, chemically amplified resist, metal oxide resist mor, resist sensitivity resolution
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
Photovoltaics: Semiconductor Junctions, Solar Cell Physics, and System Design Photovoltaic (PV) energy conversion transforms solar radiation directly into electricity via…
autonomous pd, machine learning pd, ml placement, ai eda, ml chip design
Machine Learning in Physical Design (AI-EDA) is the application of neural networks, reinforcement learning, and other ML techniques to accelerate and improve placement, routing…
block placement chip, macro placement, floorplan optimization, die area utilization
Chip Floorplanning is the critical early-stage physical design activity that determines the spatial arrangement of major functional blocks (hard macros, soft macros, memory…
chip floorplan methodology, block placement floorplan, floorplan power planning, hierarchical floorplanning
Physical Design Floorplanning is the critical early-stage physical implementation step that defines the chip's spatial organization by determining die size, placing hard macro…
block level pnr, top level integration, chip assembly
Hierarchical Physical Design is the divide-and-conquer methodology for implementing large SoCs where the chip is partitioned into independently designed blocks (macros/partitions)…
ring oscillator puf, sram puf bit, hardware fingerprint chip, puf authentication security
Physical Unclonable Functions (PUF) are a hardware security primitive that exploits manufacturing variations to generate unique, unpredictable, and unclonable per-chip secrets…
physical vapor, deposition process modeling, ml pvd, physical vapor deposition, vapor deposition process, vapor deposition, deposition process, process modeling
Physical Vapor Deposition Process Modeling Introduction & Motivation Predicting PVD process outcomes through ML accelerates film deposition development for coatings, electronics…
physical vapor deposition sputtering rate prediction, physical vapor deposition, vapor deposition sputtering, deposition sputtering rate, sputtering rate prediction
Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning Introduction & Motivation Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning…
physics modeling, differential equations, semiconductor physics, device physics, transport equations, heat transfer equations, process modeling, pde semiconductor
Physics-based semiconductor modeling converts conservation laws, material relations, geometry, and operating conditions into a boundary-value or initial-boundary-value problem…
pick-and-place accuracy, packaging
Test and packaging turn a completed wafer into a dependable product. Fabrication creates transistors and interconnect, but it does not prove that every die works, connect the die…
piezoelectric mems actuator fabrication yield prediction machine learning, piezoelectric mems, actuator fabrication yield, mems, piezoelectric mems actuator
Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine Learning Introduction & Motivation Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine…
piezoresponse force microscopy, pfm, metrology
Piezoresponse Force Microscopy (PFM) is a contact-mode scanning probe technique that maps the local piezoelectric response of a material by applying an AC voltage through…
pin diode rf switch, pin diode photodetector, pin forward bias minority carrier, pin variable resistor
PIN Diode is the p-i-n junction with intrinsic (i) layer enabling efficient photodetection and RF switching through minority carrier storage and variable resistance under forward…
pga, packaging
Pin grid array is the package architecture with pins arranged in a two-dimensional grid on the package underside for high pin-count connectivity - it supports dense interconnect…
rca clean, wafer cleaning, surface preparation, sc-1, sc-2, piranha clean, marangoni drying, clean tech
RCA cleaning and advanced semiconductor surface preparation constitute the sequential wet chemical and physical processes engineered to remove organic residues, sub-micron…
lithography pitch, contacted poly pitch, cpp, minimum metal pitch, mmp, feature pitch, pattern pitch, semiconductor pitch, node scaling, lithography
Lithography pitch is the fundamental center-to-center distance between repeating identical features on a semiconductor wafer, defining the ultimate packing density, interconnect…