3,533 technical terms and definitions
sd contact resistance, contact resistivity reduction, metal semiconductor contact, silicide contact resistance
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
sige epitaxy channel strain, raised source drain process, selective epitaxial deposition, in-situ doped epitaxy
Source/Drain Epitaxial Growth Process — Precision semiconductor crystal growth technology enabling strain engineering, junction profile optimization, and contact resistance…
sadp self-aligned double patterning, saqp self-aligned quadruple patterning, spacer patterning pitch splitting, sidewall spacer lithography, sadp, saqp
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
spare parts first wafer yield risk prediction, spare parts first, parts first wafer, first wafer yield, wafer yield risk, yield risk prediction, spare parts, parts first
Spare Parts First Wafer Yield Risk Prediction with Machine Learning Introduction & Motivation Spare Parts First Wafer Yield Risk Prediction with Machine Learning addresses…
semiconductor spare parts, spare parts optimization, spare parts stocking levels, fab spare parts management
Spare parts inventory management strategically stocks replacement components near semiconductor fabrication tools to minimize mean-time-to-repair (MTTR) and fab downtime.…
spatial computing hardware, spatial architecture, cgra, wafer scale engine, dataflow processor
Spatial computing definition and engineering boundary. in hardware architecture places many operations and storage resources at distinct physical locations and configures data…
spatial kriging wafer metrology interpolation machine learning, spatial kriging, wafer metrology interpolation, spatial kriging for wafer metrology interpolation
Spatial Kriging for Wafer Metrology Interpolation with Machine Learning Introduction & Motivation Spatial Kriging for Wafer Metrology Interpolation with Machine Learning addresses…
metrology
Spatial signature is the characteristic pattern of failures on a wafer — the unique fingerprint of a process issue, equipment problem, or systematic defect that appears…
spatial wafer level yield model prediction with machine learning, spatial wafer level yield model prediction machine learning, spatial wafer, level yield model, yield model
Spatial Wafer-Level Yield Model Prediction with Machine Learning Introduction & Motivation Spatial Wafer-Level Yield Model Prediction with Machine Learning addresses a central…
thin film ellipsometer, refractive index dispersion n k, delta psi ellipsometry, cauchy lorentz oscillator model, sub angstrom optical film metrology
Spectroscopic ellipsometry measures how reflection changes the polarization of light across a wavelength range and uses that information to infer thin-film thickness, complex…
manufacturing equipment, optical metrology, thin film measurement, refractive index n k, dispersion model, surface roughness measurement
Spectroscopic ellipsometry measures how reflection changes the polarization of light across a wavelength range and uses that information to infer thin-film thickness, complex…
ellipsometry wafer mapping, ellipsometric thickness mapping, spectroscopic ellipsometry map, wafer optical constants mapping, imaging ellipsometry mapping, ellipsometry mapping metrology
Spectroscopic ellipsometry mapping converts polarization changes at registered positions into spatial models of film thickness, optical constants, roughness, composition, or other…
keyword spotting chip, neural engine voice, always on audio processor, wake word detection chip
Speech and Audio Processing Chip: Always-On Keyword Spotting Engine — ultra-low-power neural network for wake-word detection enabling voice assistant activation with <1 mW standby…
serial peripheral interface, sclk, mosi, miso, chip select, qspi, ospi, spi bus
SPI protocol is a synchronous serial interface in which a controller supplies clock and chip select while exchanging data over separate output and input lines. Its simple…
spiking neural network chip yield prediction, spiking neural network, neural network chip, network chip yield, chip yield prediction, spiking neural, neural network, chip yield
Spiking Neural Network Chip Yield Prediction with Machine Learning Introduction & Motivation Spiking Neural Network Chip Yield Prediction with Machine Learning addresses a central…
Spin Hall Effect, Rashba-Edelstein Kinetics, Spin Accumulation, and Harmonic Hall Metrology 1. Introduction: Spin-Orbit Coupling and Spintronics Spin-orbit coupling (SOC) is…
semiconductor spin qubit quantum dot silicon germanium exchange coupling J, singlet triplet S T0 qubit spin relaxation T1 dephasing T2 star
Semiconductor Spin Qubits: Exchange Coupling, Singlet-Triplet Dynamics, and Pauli Spin Blockade 1. Introduction: Spin Qubits in Silicon and Germanium Semiconductor spin…
metrology
Split-CV (Split Capacitance-Voltage) is the semiconductor metrology technique that quantifies interface state density (Dit) at the insulator-semiconductor interface by measuring…
sputter chamber shield redeposition prediction machine learning, sputter chamber, shield redeposition prediction, pvd, sputter chamber shield redeposition prediction
Sputter Chamber Shield Redeposition Prediction with Machine Learning Introduction & Motivation Sputter Chamber Shield Redeposition Prediction with Machine Learning addresses…
sputter deposition step coverage prediction machine learning, sputter deposition, step coverage prediction, pvd, sputter deposition step coverage prediction, deposition step
Sputter Deposition Step Coverage Prediction with Machine Learning Introduction & Motivation Sputter Deposition Step Coverage Prediction with Machine Learning addresses a central…
pvd sputtering, sputtering process, physical sputtering, sputter deposition, sputtered film, sputtering mechanism, sputtering pressure, sputtering gas scattering, sputtering angular distribution, sputtered atom energy, sputtering film stress
Sputtering converts ion energy at a solid target into a transported flux of atoms, clusters, reflected neutrals, electrons, photons, and sometimes ions that build a film on…
sraf, sub-resolution assist features, lithography
Sub-Resolution Assist Features (SRAFs) are tiny patterns placed on the photomask near main features that are too small to print on the wafer but improve the imaging quality of…
sram bitcell scaling, sram read write margin, 6t sram stability, sram vmin
SRAM Scaling and Yield is the canary-in-the-coalmine indicator for semiconductor process health — where the densest, most variation-sensitive circuit on the chip (the 6-transistor…
metrology
Stability in metrology is the consistency of measurement results obtained on the same part over an extended period of time — tracking whether a semiconductor metrology tool's…
metrology
Stability in metrology is the consistency of measurement results over time — a stable measurement system produces the same results today, next week, and next month when measuring…
3d transistor stacking, monolithic 3d integration, sequential transistor fabrication, tier bonding process
Stacked Transistor Integration is the advanced manufacturing approach that creates multiple active device layers in the vertical dimension through sequential fabrication or layer…
staining, defect, metrology
Staining (Defect Delineation) is a wet-chemical or electrochemical technique that creates optical contrast between semiconductor regions of different doping type, concentration…
packaging
Standoff height is the distance between the bottom of the package body and the PCB surface after mounting - it influences solder-joint shape, cleaning access, and thermomechanical…
noise margin design, glitch analysis, functional noise chip, noise propagation
Static Noise Analysis (SNA) is the technique for verifying that noise on internal chip signals does not cause functional failures — analyzing whether signal disturbances…
static sims metrology, static secondary ion mass spectrometry, surface static sims
Static SIMS (secondary ion mass spectrometry) is the low-dose regime of surface static SIMS analysis in which the primary ion beam is held far below the fluence that would…
statistical mechanics, statistical physics, thermodynamic ensembles, partition function, boltzmann distribution, quantum statistics, fermi dirac, bose einstein, semiconductor statistical mechanics
Statistical mechanics explains macroscopic matter by treating microscopic states probabilistically. Instead of following every atom, electron, phonon, spin, or defect, it defines…
stem, metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
lithography
A Stepper is a lithography tool that projects a reticle (mask) pattern onto photoresist-coated wafers using a step-and-repeat process — exposing one die (or a small group of dies)…
packaging
Stitch bond is the second wire-bond connection formed by pressing wire onto substrate or lead without forming a free-air ball - it completes the electrical path after the first…
lithography
Stochastic defects are random, unpredictable patterning failures caused by the statistical nature of photoresist chemistry at the nanoscale. Unlike systematic defects (which occur…
lithography
Stochastic Effects in Lithography are random, statistically distributed variations in photon absorption and photochemical reactions in photoresist that produce local pattern…
stokes anti-stokes raman, spontaneous anti-stokes raman, stokes anti-stokes ratio, raman thermometry, anti-stokes thermometry, stokes anti-stokes metrology
Stokes and anti-Stokes Raman bands are mirror-side energy exchanges around the laser line, but they are not automatically mirror images in measured intensity. In Stokes…
raman stress calibration, raman strain calibration, phonon deformation potential calibration, semiconductor stress mapping calibration, spectroscopic stress calibration, stress strain metrology
Stress–strain calibration is the chain that converts a measured spectral or diffraction change into a mechanical quantity with defined units, sign, orientation, spatial weighting…
metrology
Stylus profilometer is a surface measurement instrument that drags a fine-tipped diamond stylus across a surface to measure its topography — providing direct, traceable…
first silicon success, first silicon, success, working chips, yield rate
Chip Foundry Services achieves 95%+ first-silicon success rate — meaning 95% of our designs work correctly on first fabrication compared to 60-70% industry average, with our…
business
Supply Chain for Chiplets is the multi-vendor ecosystem of design houses, foundries, packaging providers, and test facilities that must coordinate to produce multi-die…
wafer processing optimizing surface activation for direct bonding processes, wafer processing optimizing, processing optimizing surface, optimizing surface activation, wafer processing
Wafer Processing: Optimizing surface activation for direct bonding processes Introduction & Motivation Wafer Processing: Optimizing surface activation for direct bonding processes…
larger contact area lowers mechanical stress bonding, thermal barrier budget independent of contact area, surface barrier cumulative wafer stress remaining margin
Attach the Collector Lead: More Margin on This Face, Less Margin Left in the Wafer This step applies the identical dual constraint step nineteen established — stay under…
metal semiconductor rectifying contact schottky barrier, work function electron affinity barrier height phi_b, surface barrier device name comes from this contact
Electroplate the Collector Into the Bottom Pit: Where This Device's Name Actually Comes From Every junction this project has documented before this step — point-contact's…
stop time mismatch mirror of start time error, diffusion limited residual dissolution after current cutoff, surface barrier two sequential actions current then flush
Halt Etching at Target Base Thickness: Why Stopping Has the Same Timing Problem Starting Did Step fourteen's monitoring circuit detects the moment current reaches , but detecting…
faraday law etch rate current independent circuits, start time offset depth mismatch delta t start, surface barrier timing tolerance shrinks faster etch rate
Initiate Simultaneous Top and Bottom Etching: Why the Two Jets Must Start Together, Not Just Aim Together Step eleven aligned the two jets on a shared point, and step twelve…
shared alignment margin fixture concentricity placement error, usable region defect exclusion zone correct placement, surface barrier as built fixture measurement not nominal tolerance
Position the Wafer Within the Fixture: Spending Step Ten's Margin for the First Time Step eleven built a fixture whose two jets already agree on a shared point in space; this step…
membrane fracture stress force budget rinse, wetting requirement unchanged gentler rinse procedure, surface barrier trading force for time cleaning
Rinse the Etched Wafer: Cleaning a Surface That Can No Longer Absorb a Rough Touch Step nine already established that this process's surfaces have to wet an electrolyte and later…
wafer thickness kerf loss saw cut yield tradeoff, base width ceiling etch pit depth top bottom, surface barrier thickness ceiling spent by etching not firing
Slice the Germanium: The Same Ceiling, Now Approached From Both Faces by Etching Instead of One Pair of Firing Depths Slicing here is the same pure geometry-and-yield problem…
surface barrier transistor electrochemical etching, electroplate metal contacts germanium base thinning, 1953 surface barrier transistor fragile low power, thin base transit time megahertz frequency
The Surface-Barrier Transistor: Jet-Etching a Base Thin Enough to Reach Tens of Megahertz The surface-barrier transistor, introduced by Philco in 1953 (with General Electric…