27,049 technical terms and definitions
immersion lithography explained, water immersion lithography meaning, duv immersion, immersion lithography vs euv
Immersion lithography is a technique that places a thin layer of purified water between the lens and the wafer during DUV lithography, using water's optical properties to bend…
ion implantation explained, semiconductor doping process, boron phosphorus arsenic dopant, spike anneal activation, source drain junction implant
Ion implantation is how a fab actually changes silicon's electrical personality, not just its shape. Etch and CVD sculpt and build up physical structure, but neither one turns…
IR drop is the reduction in voltage that occurs as current flows through the resistance of a chip's power distribution network, meaning circuits located farther from the power…
Knowledge distillation is a machine learning technique where a smaller, more efficient model is trained to mimic the outputs of a larger, more capable model, transferring much…
what is a KGD
A known good die, or KGD, is a die that has been electrically tested and verified to meet its full performance and quality specifications before being assembled into a package…
ler lithography explained, line edge roughness meaning, chip manufacturing edge roughness, what does ler mean
Line edge roughness, or LER, refers to the small, irregular waviness along the edges of a patterned feature on a chip — instead of a perfectly smooth, straight line, real…
prefill vs decode explained, kv cache transformer, roofline model ai accelerator, llm serving throughput latency, memory bandwidth bound inference
LLM inference is running an already-trained model forward to answer a live request, and it behaves nothing like training on the hardware underneath it. Training adjusts a model's…
Massive MIMO, or massive multiple-input multiple-output, is a wireless technology that equips a base station with a very large number of antennas, letting it serve many users…
semiconductor metrology explained, wafer inspection defect detection, CD-SEM overlay scatterometry, statistical process control fab, OCD critical dimension measurement
Metrology and inspection are how a fab knows whether the last 60 process steps actually worked, without waiting until the finished chip fails to find out. After nearly every…
mmwave explained, millimeter wave 5g meaning, mmwave vs sub-6, what does mmwave mean
Millimeter wave, often called mmWave, refers to a very high-frequency band of radio spectrum used by some 5G networks, offering dramatically more available bandwidth and faster…
mimo wireless explained, mimo meaning 5g, multiple input multiple output, what does mimo stand for
MIMO, short for multiple-input multiple-output, is a wireless technology that uses multiple antennas at both the transmitter and receiver to send and receive several data streams…
mixed precision training explained, ai training precision meaning, mixed precision ai model, what does mixed precision mean
Mixed precision training is a technique for training AI models that uses lower-precision numbers for most calculations to gain speed and memory savings, while selectively keeping…
moe llm architecture explained, sparse expert routing, moe vs dense model, expert router transformer, moe memory capacity accelerator
Mixture-of-experts (MoE) is an architecture where a model has far more total parameters than a comparably-sized dense model, but only activates a small fraction of them for any…
MOCVD, or metal-organic chemical vapor deposition, is a specialized deposition technique that uses metal-organic precursor gases to grow high-quality crystalline compound…
ai model distillation explained, knowledge distillation meaning, teacher student model ai, what does model distillation mean
Model distillation is a technique for training a smaller, faster "student" AI model to mimic the behavior of a larger, more capable "teacher" model, transferring much of…
model quantization explained, ai model quantization meaning, quantization neural network, why quantize ai models
Model quantization is a technique that shrinks an AI model by representing its internal numbers with less precision — for example, using 8-bit values instead of the 32-bit values…
moore's law explained, moores law meaning, is moores law dead, moores law transistor count
Moore's Law is the observation, made by Intel co-founder Gordon Moore in 1965, that the number of transistors that can be economically packed onto a chip roughly doubles every…
Multi-patterning is a lithography technique that splits a single densely packed layer's pattern across multiple separate exposure and etch steps, achieving finer feature spacing…
Network function virtualization, or NFV, is an approach that replaces dedicated hardware appliances for network functions like firewalls or routers with software running on…
Network slicing is a 5G capability that lets a single physical network be divided into multiple separate, virtual networks, each independently configured and tuned for a different…
non-recurring engineering cost, chip nre explained, semiconductor nre meaning, nre vs per-unit cost
Non-recurring engineering cost, or NRE cost, refers to the one-time upfront expense of designing and preparing a chip for manufacturing — covering things like design work…
opc lithography explained, optical proximity correction meaning, computational lithography opc, what does opc mean in chip manufacturing
Optical proximity correction, or OPC, is a computational technique that deliberately distorts the pattern on a photomask in precise, calculated ways so that after light…
what is out of order execution
Out-of-order execution is a processor design technique where instructions are allowed to run in whatever order their inputs become ready, rather than strictly in the order they…
photoresist explained, photoresist lithography meaning, positive vs negative photoresist, how does photoresist work
Photoresist is a light-sensitive chemical coating applied to a silicon wafer before lithography, one that chemically changes when exposed to light so that, after development, it…
plasma etching explained, RIE vs ICP etch, anisotropic etch semiconductor, dry etch process chip fabrication, plasma etch selectivity endpoint
Plasma etch is how a chip factory carves the pattern from a photomask into the actual silicon, layer by layer. After lithography exposes a resist pattern on the wafer, that…
Plasma etching is a fabrication process that uses a chemically reactive, ionized gas to remove material from a wafer's surface in a controlled pattern, enabling the fine…
poly gate etch explained, gate critical dimension control, polysilicon gate fabrication, gate etch stop on oxide, transistor gate patterning
Polysilicon etch is the process step that carves polycrystalline silicon into precise gate shapes, and for decades it was the single most critical etch step in the entire fab…
int8 fp8 int4 explained, llm quantization accuracy tradeoff, weight only quantization, activation quantization inference, quantization memory bandwidth ai accelerator
Quantization is the practice of storing and computing a model's weights and activations in fewer bits than the 16 or 32 bits they were trained in, trading a small amount…
Quantization-aware training is a technique that simulates the effects of reduced numerical precision during a neural network's training process itself, letting the model adapt…
quantum computing explained, what is a qubit, quantum computing meaning, quantum vs classical computing
Quantum computing is a fundamentally different approach to computation that uses quantum bits, or "qubits," instead of the ordinary bits every classical chip relies on — where…
ram explained, ram vs storage, random access memory, how does ram work
RAM, or random access memory, is the fast, temporary workspace a computer uses to hold whatever it's actively working on — open programs, loaded data, the current state of a game…
Rapid thermal annealing, or RTA, is a process that briefly heats a wafer to a high temperature for only seconds at a time, used to activate dopants and repair implant damage…
Reinforcement learning is a way of training an AI system by letting it take actions in an environment and learn from the resulting rewards or penalties — rather than learning…
what is RAG AI
Retrieval-augmented generation, or RAG, is a technique that combines a language model with an external search step, retrieving relevant documents or facts from an outside…
Setup and hold time are the two timing constraints that define the window around a clock edge during which a flip-flop's input data must remain stable, with setup time covering…
what is STI
Shallow trench isolation, or STI, is the technique used to electrically separate neighboring transistors on a chip by etching a narrow trench between them and filling it…
sti semiconductor explained, transistor isolation fab process, sti etch fill cmp, front end of line isolation, sti trench oxide fill
Shallow trench isolation (STI) is the structure that keeps neighboring transistors electrically separate, and it's one of the earliest steps in the front-end-of-line process that…
Silicide is a compound formed by reacting a metal with silicon at the transistor's contact regions, creating a layer with much lower electrical resistance than silicon alone…
SIMD, or Single Instruction Multiple Data, is a processor technique that applies one instruction to many pieces of data simultaneously, rather than repeating that same instruction…
draft model verification llm, speculative sampling explained, llm decode throughput optimization, draft and verify inference, accelerated token generation
Speculative decoding is a way to generate multiple tokens per expensive decode step instead of just one, by letting a small, cheap "draft" model guess ahead and having the large…
Static timing analysis, or STA, is a verification technique that checks whether every signal path in a chip design can meet its required timing without needing to simulate…
Strained silicon is a technique that deliberately stretches or compresses the silicon crystal lattice in a transistor's channel region, altering how easily electrons or holes move…
Subthreshold slope is a measure of how sharply a transistor's current turns off as its gate voltage drops below the threshold needed to switch it on, with a steeper, lower slope…
Tensor parallelism is a technique that splits an individual neural network layer's own weight matrices across multiple devices, letting each device compute part of the same…
universal chiplet interconnect express, die to die interconnect standard, chiplet interoperability standard, ucie physical layer protocol layer, pcie cxl chiplet
UCIe (Universal Chiplet Interconnect Express) is the standardized protocol that lets chiplets from different vendors, built on different process nodes, actually talk to each other…
Underfill is a specialized epoxy material injected into the tiny gap between a flip-chip die and its substrate after solder bump bonding, mechanically reinforcing those solder…
Wafer bonding is a process that joins two separately processed wafers face to face into a single mechanically and often electrically connected structure, enabling…
Wafer dicing is the process of physically cutting a finished, fully tested wafer apart into its individual chips, separating the many identical dies that were manufactured…
wafer probe test explained, dicing singulation semiconductor, chip packaging types, CoWoS advanced packaging, HBM TSV stacking, known good die
Once the last metal layer is done, a finished wafer is still just a fragile glass-thin disc holding hundreds of identical, untested chips. Everything up to this point…
Wafer thinning is a process that mechanically and chemically reduces a finished wafer's thickness, often down to a fraction of its original size, to enable thin chip packaging, 3D…